diff options
Diffstat (limited to 'src/soc/rockchip')
| -rw-r--r-- | src/soc/rockchip/rk3399/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3399/bootblock.c | 1 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3399/clock.c | 6 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3399/include/soc/clock.h | 2 |
4 files changed, 6 insertions, 5 deletions
diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc index 6e7527893c..ceec7bc29f 100644 --- a/src/soc/rockchip/rk3399/Makefile.inc +++ b/src/soc/rockchip/rk3399/Makefile.inc @@ -23,10 +23,12 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c endif bootblock-y += ../common/gpio.c +bootblock-y += ../common/pwm.c bootblock-y += bootblock.c bootblock-y += clock.c bootblock-y += gpio.c bootblock-y += mmu_operations.c +bootblock-y += saradc.c bootblock-y += timer.c verstage-y += ../common/cbmem.c diff --git a/src/soc/rockchip/rk3399/bootblock.c b/src/soc/rockchip/rk3399/bootblock.c index 4f85e94ff4..7b80a75e33 100644 --- a/src/soc/rockchip/rk3399/bootblock.c +++ b/src/soc/rockchip/rk3399/bootblock.c @@ -22,7 +22,6 @@ void bootblock_soc_init(void) { rkclk_init(); - rkclk_configure_cpu(APLL_600_MHZ, false); /* all ddr range non-secure */ write32(&rk3399_pmusgrf->ddr_rgn_con[16], 0xff << 16 | 0); diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index ed9afda3ca..428a210e00 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -47,11 +47,11 @@ static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); -static const struct pll_div apll_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1); -static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); +static const struct pll_div apll_1512_cfg = PLL_DIVISORS(1512*MHz, 1, 1, 1); +static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 3, 1); static const struct pll_div *apll_cfgs[] = { - [APLL_1600_MHZ] = &apll_1600_cfg, + [APLL_1512_MHZ] = &apll_1512_cfg, [APLL_600_MHZ] = &apll_600_cfg, }; diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h index 19e315b8da..de86ed42a9 100644 --- a/src/soc/rockchip/rk3399/include/soc/clock.h +++ b/src/soc/rockchip/rk3399/include/soc/clock.h @@ -97,7 +97,7 @@ static struct rk3399_cru_reg * const cru_ptr = (void *)CRU_BASE; #define PWM_CLOCK_HZ PMU_PCLK_HZ enum apll_frequencies { - APLL_1600_MHZ, + APLL_1512_MHZ, APLL_600_MHZ, }; |