4 files changed, 54 insertions, 85 deletions

diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig
index 05876f4f0b..0865fe8f54 100644
--- a/src/soc/rockchip/rk3288/Kconfig
+++ b/src/soc/rockchip/rk3288/Kconfig
@@ -41,51 +41,6 @@ config BOOTBLOCK_CPU_INIT
 # 0x00000 Combined bootblock and ID Block
 # 0x08000 Master CBFS header.
 # 0x18000 Free for CBFS data.
-#
-# iRAM (96k) layout.
-# (Note: The BootROM will jump to 0xff704004 after loading bootblock,
-#  so the bootblock loading address must be at 0xff704004.)
-#
-# 0xFF70_0000 TTB (16KB).
-# 0xFF70_4004 Bootblock (max 16KB-4B).
-# 0xFF70_8000 verstage then romstage (max 40KB).
-# 0xFF71_2000 STACK (4KB).
-# 0xFF71_3000 CBFS mapping cache (4K)
-# 0xFF71_4000 vboot work buffer (16K)
-# 0xFF71_7FFF End of iRAM.
-
-config SYS_SRAM_BASE
-	hex "SRAM base address"
-	default 0xFF700000
-
-config SYS_SDRAM_BASE
-	hex "SDRAM base address"
-	default 0x00000000
-
-config STACK_TOP
-	hex "STACK TOP"
-	default 0xff713000
-
-config STACK_BOTTOM
-	hex "STACK BOTTOM"
-	default 0xff712000
-
-config BOOTBLOCK_BASE
-	hex
-	default 0xff704004
-
-# with vboot2, romstage is loaded over the verstage space
-config VERSTAGE_BASE
-	hex
-	default 0xff708000
-
-config ROMSTAGE_BASE
-	hex "ROM STAGE BASE"
-	default 0xff708000
-
-config RAMSTAGE_BASE
-	hex "RAMSTAGE BASE"
-	default 0x00200000
 
 config BOOTBLOCK_ROM_OFFSET
 	hex
@@ -99,32 +54,4 @@ config CBFS_ROM_OFFSET
 	hex
 	default 0x0018000
 
-config CBFS_SRAM_CACHE_ADDRESS
-	hex "sram memory address to put CBFS cache data"
-	default 0xff713000
-
-config CBFS_SRAM_CACHE_SIZE
-	hex "size of CBFS cache data"
-	default 0x00001000
-
-config VBOOT_WORK_BUFFER_ADDRESS
-	hex "memory address of vboot work buffer"
-	default 0xff714000
-
-config VBOOT_WORK_BUFFER_SIZE
-	hex "size of vboot work buffer"
-	default 0x00004000
-
-config CBFS_DRAM_CACHE_ADDRESS
-	hex "dram memory address to put CBFS cache data"
-	default 0x01000000
-
-config CBFS_DRAM_CACHE_SIZE
-	hex "size of CBFS cache data"
-	default 0x00100000
-
-config TTB_BUFFER
-	hex "memory address of the TTB buffer"
-	default 0xff700000
-
 endif
diff --git a/src/soc/rockchip/rk3288/media.c b/src/soc/rockchip/rk3288/media.c
index 2b023e15df..f2471f9b5a 100644
--- a/src/soc/rockchip/rk3288/media.c
+++ b/src/soc/rockchip/rk3288/media.c
@@ -18,19 +18,12 @@
  */
 
 #include <cbfs.h>
-#include <string.h>
-#include <console/console.h>
-#include "soc/rockchip/rk3288/spi.h"
+#include <symbols.h>
+
+#include "spi.h"
 
 int init_default_cbfs_media(struct cbfs_media *media)
 {
-#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__)
-	return initialize_rockchip_spi_cbfs_media(media,
-		(void *)CONFIG_CBFS_SRAM_CACHE_ADDRESS,
-		CONFIG_CBFS_SRAM_CACHE_SIZE);
-#else
 	return initialize_rockchip_spi_cbfs_media(media,
-		(void *)CONFIG_CBFS_DRAM_CACHE_ADDRESS,
-		CONFIG_CBFS_DRAM_CACHE_SIZE);
-#endif
+		_cbfs_cache, _cbfs_cache_size);
 }
diff --git a/src/soc/rockchip/rk3288/memlayout.ld b/src/soc/rockchip/rk3288/memlayout.ld
new file mode 100644
index 0000000000..6faec63ba5
--- /dev/null
+++ b/src/soc/rockchip/rk3288/memlayout.ld
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <memlayout.h>
+#include <vendorcode/google/chromeos/memlayout.h>
+
+#include <arch/header.ld>
+
+/* Note: The BootROM will jump to 0xFF704004 after loading bootblock,
+ * so the bootblock loading address must be at 0xFF704004.
+ */
+SECTIONS
+{
+	DRAM_START(0x00000000)
+	RAMSTAGE(0x00200000, 128K)
+	POSTRAM_CBFS_CACHE(0x01000000, 1M)
+	DMA_COHERENT(0x10000000, 2M)
+
+	SRAM_START(0xFF700000)
+	TTB(0xFF700000, 16K)
+	BOOTBLOCK(0xFF704004, 16K - 4)
+	VBOOT2_WORK(0xFF708000, 16K)
+	OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C000, 40K)
+	PRERAM_CBFS_CACHE(0xFF716000, 4K)
+	STACK(0xFF717000, 4K)
+	SRAM_END(0xFF718000)
+
+	/* 4K of special SRAM in PMU power domain. Careful: only supports 32-bit
+	 * wide write accesses! Only use with MMU and writeback mapping. */
+	SYMBOL(pmu_sram, 0xFF720000)
+	SYMBOL(epmu_sram, 0xFF721000)
+}
diff --git a/src/soc/rockchip/rk3288/soc.h b/src/soc/rockchip/rk3288/soc.h
index 3121fd872d..00f35b2f3c 100644
--- a/src/soc/rockchip/rk3288/soc.h
+++ b/src/soc/rockchip/rk3288/soc.h
@@ -21,13 +21,14 @@
 #define __SOC_ROCKCHIP_RK3288_CPU_H__
 
 #include <arch/io.h>
+#include <symbols.h>
 
 #define RK_CLRSETBITS(clr, set) ((((clr) | (set)) << 16) | set)
 #define RK_SETBITS(set) RK_CLRSETBITS(0, set)
 #define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0)
 
 #define FB_SIZE_KB  4096
-#define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10)
+#define RAM_BASE_KB ((uintptr_t)_dram >> 10)
 #define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL)
 
 static inline u32 get_fb_base_kb(void)