diff options
Diffstat (limited to 'src/soc/rockchip/rk3288/include')
| -rw-r--r-- | src/soc/rockchip/rk3288/include/soc/clock.h | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/soc/rockchip/rk3288/include/soc/clock.h b/src/soc/rockchip/rk3288/include/soc/clock.h index 08d9d45a3f..3fccecb8f2 100644 --- a/src/soc/rockchip/rk3288/include/soc/clock.h +++ b/src/soc/rockchip/rk3288/include/soc/clock.h @@ -24,11 +24,15 @@ #define OSC_HZ (24*MHz) -#define APLL_HZ (1800*MHz) #define GPLL_HZ (594*MHz) #define CPLL_HZ (384*MHz) #define NPLL_HZ (384*MHz) +enum apll_frequencies { + APLL_1800_MHZ, + APLL_1392_MHZ, +}; + /* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed. */ #define PD_BUS_ACLK_HZ (297000*KHz) #define PD_BUS_HCLK_HZ (148500*KHz) @@ -44,7 +48,7 @@ void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy); void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n); void rkclk_configure_ddr(unsigned int hz); void rkclk_configure_i2s(unsigned int hz); -void rkclk_configure_cpu(void); +void rkclk_configure_cpu(enum apll_frequencies apll_freq); void rkclk_configure_crypto(unsigned int hz); void rkclk_configure_tsadc(unsigned int hz); void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz); |