diff options
Diffstat (limited to 'src/soc/rockchip/rk3288/clock.c')
| -rw-r--r-- | src/soc/rockchip/rk3288/clock.c | 161 |
1 files changed, 64 insertions, 97 deletions
diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index d7420ea8d6..a9c888d631 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -217,19 +217,20 @@ static int rkclk_set_pll(u32 *pll_con, const struct pll_div *div) (div->no == 1 || !(div->no % 2))); /* enter rest */ - writel(RK_SETBITS(PLL_RESET_MSK), &pll_con[3]); + write32(&pll_con[3], RK_SETBITS(PLL_RESET_MSK)); - writel(RK_CLRSETBITS(PLL_NR_MSK, (div->nr - 1) << PLL_NR_SHIFT) - | RK_CLRSETBITS(PLL_OD_MSK, (div->no - 1)), &pll_con[0]); + write32(&pll_con[0], + RK_CLRSETBITS(PLL_NR_MSK, (div->nr - 1) << PLL_NR_SHIFT) | RK_CLRSETBITS(PLL_OD_MSK, (div->no - 1))); - writel(RK_CLRSETBITS(PLL_NF_MSK, (div->nf - 1)), &pll_con[1]); + write32(&pll_con[1], RK_CLRSETBITS(PLL_NF_MSK, (div->nf - 1))); - writel(RK_CLRSETBITS(PLL_BWADJ_MSK, ((div->nf >> 1) - 1)), &pll_con[2]); + write32(&pll_con[2], + RK_CLRSETBITS(PLL_BWADJ_MSK, ((div->nf >> 1) - 1))); udelay(10); /* return form rest */ - writel(RK_CLRBITS(PLL_RESET_MSK), &pll_con[3]); + write32(&pll_con[3], RK_CLRBITS(PLL_RESET_MSK)); return 0; } @@ -257,9 +258,8 @@ void rkclk_init(void) u32 pclk_div; /* pll enter slow-mode */ - writel(RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_SLOW) - | RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_SLOW), - &cru_ptr->cru_mode_con); + write32(&cru_ptr->cru_mode_con, + RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_SLOW) | RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_SLOW)); /* init pll */ rkclk_set_pll(&cru_ptr->cru_gpll_con[0], &gpll_init_cfg); @@ -267,7 +267,7 @@ void rkclk_init(void) /* waiting for pll lock */ while (1) { - if ((readl(&rk3288_grf->soc_status[1]) + if ((read32(&rk3288_grf->soc_status[1]) & (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) == (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) break; @@ -288,15 +288,8 @@ void rkclk_init(void) assert((pclk_div + 1) * PD_BUS_PCLK_HZ == PD_BUS_ACLK_HZ && pclk_div < 0x7); - writel(RK_SETBITS(PD_BUS_SEL_GPLL) - | RK_CLRSETBITS(PD_BUS_PCLK_DIV_MSK, - pclk_div << PD_BUS_PCLK_DIV_SHIFT) - | RK_CLRSETBITS(PD_BUS_HCLK_DIV_MSK, - hclk_div << PD_BUS_HCLK_DIV_SHIFT) - | RK_CLRSETBITS(PD_BUS_ACLK_DIV0_MASK, - aclk_div << PD_BUS_ACLK_DIV0_SHIFT) - | RK_CLRSETBITS(PD_BUS_ACLK_DIV1_MASK, 0 << 0), - &cru_ptr->cru_clksel_con[1]); + write32(&cru_ptr->cru_clksel_con[1], + RK_SETBITS(PD_BUS_SEL_GPLL) | RK_CLRSETBITS(PD_BUS_PCLK_DIV_MSK, pclk_div << PD_BUS_PCLK_DIV_SHIFT) | RK_CLRSETBITS(PD_BUS_HCLK_DIV_MSK, hclk_div << PD_BUS_HCLK_DIV_SHIFT) | RK_CLRSETBITS(PD_BUS_ACLK_DIV0_MASK, aclk_div << PD_BUS_ACLK_DIV0_SHIFT) | RK_CLRSETBITS(PD_BUS_ACLK_DIV1_MASK, 0 << 0)); /* * peri clock pll source selection and @@ -313,33 +306,26 @@ void rkclk_init(void) assert((1 << pclk_div) * PERI_PCLK_HZ == PERI_ACLK_HZ && (pclk_div < 0x4)); - writel(RK_SETBITS(PERI_SEL_GPLL) - | RK_CLRSETBITS(PERI_PCLK_DIV_MSK, - pclk_div << PERI_PCLK_DIV_SHIFT) - | RK_CLRSETBITS(PERI_HCLK_DIV_MSK, - hclk_div << PERI_HCLK_DIV_SHIFT) - | RK_CLRSETBITS(PERI_ACLK_DIV_MSK, - aclk_div << PERI_ACLK_DIV_SHIFT), - &cru_ptr->cru_clksel_con[10]); + write32(&cru_ptr->cru_clksel_con[10], + RK_SETBITS(PERI_SEL_GPLL) | RK_CLRSETBITS(PERI_PCLK_DIV_MSK, pclk_div << PERI_PCLK_DIV_SHIFT) | RK_CLRSETBITS(PERI_HCLK_DIV_MSK, hclk_div << PERI_HCLK_DIV_SHIFT) | RK_CLRSETBITS(PERI_ACLK_DIV_MSK, aclk_div << PERI_ACLK_DIV_SHIFT)); /* PLL enter normal-mode */ - writel(RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_NORM) - | RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_NORM), - &cru_ptr->cru_mode_con); + write32(&cru_ptr->cru_mode_con, + RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_NORM) | RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_NORM)); } void rkclk_configure_cpu(void) { /* pll enter slow-mode */ - writel(RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_SLOW), - &cru_ptr->cru_mode_con); + write32(&cru_ptr->cru_mode_con, + RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_SLOW)); rkclk_set_pll(&cru_ptr->cru_apll_con[0], &apll_init_cfg); /* waiting for pll lock */ while (1) { - if (readl(&rk3288_grf->soc_status[1]) & SOCSTS_APLL_LOCK) + if (read32(&rk3288_grf->soc_status[1]) & SOCSTS_APLL_LOCK) break; udelay(1); } @@ -350,24 +336,19 @@ void rkclk_configure_cpu(void) * core clock select apll, apll clk = 1800MHz * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz */ - writel(RK_CLRBITS(CORE_SEL_PLL_MSK) - | RK_CLRSETBITS(A12_DIV_MSK, 0 << A12_DIV_SHIFT) - | RK_CLRSETBITS(MP_DIV_MSK, 3 << MP_DIV_SHIFT) - | RK_CLRSETBITS(M0_DIV_MSK, 1 << 0), - &cru_ptr->cru_clksel_con[0]); + write32(&cru_ptr->cru_clksel_con[0], + RK_CLRBITS(CORE_SEL_PLL_MSK) | RK_CLRSETBITS(A12_DIV_MSK, 0 << A12_DIV_SHIFT) | RK_CLRSETBITS(MP_DIV_MSK, 3 << MP_DIV_SHIFT) | RK_CLRSETBITS(M0_DIV_MSK, 1 << 0)); /* * set up dependent divisors for L2RAM/ATCLK and PCLK clocks. * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz */ - writel(RK_CLRSETBITS(L2_DIV_MSK, 1 << 0) - | RK_CLRSETBITS(ATCLK_DIV_MSK, (3 << ATCLK_DIV_SHIFT)) - | RK_CLRSETBITS(PCLK_DBG_DIV_MSK, (3 << PCLK_DBG_DIV_SHIFT)), - &cru_ptr->cru_clksel_con[37]); + write32(&cru_ptr->cru_clksel_con[37], + RK_CLRSETBITS(L2_DIV_MSK, 1 << 0) | RK_CLRSETBITS(ATCLK_DIV_MSK, (3 << ATCLK_DIV_SHIFT)) | RK_CLRSETBITS(PCLK_DBG_DIV_MSK, (3 << PCLK_DBG_DIV_SHIFT))); /* PLL enter normal-mode */ - writel(RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_NORM), - &cru_ptr->cru_mode_con); + write32(&cru_ptr->cru_mode_con, + RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_NORM)); } void rkclk_configure_ddr(unsigned int hz) @@ -392,21 +373,21 @@ void rkclk_configure_ddr(unsigned int hz) } /* pll enter slow-mode */ - writel(RK_CLRSETBITS(DPLL_MODE_MSK, DPLL_MODE_SLOW), - &cru_ptr->cru_mode_con); + write32(&cru_ptr->cru_mode_con, + RK_CLRSETBITS(DPLL_MODE_MSK, DPLL_MODE_SLOW)); rkclk_set_pll(&cru_ptr->cru_dpll_con[0], &dpll_cfg); /* waiting for pll lock */ while (1) { - if (readl(&rk3288_grf->soc_status[1]) & SOCSTS_DPLL_LOCK) + if (read32(&rk3288_grf->soc_status[1]) & SOCSTS_DPLL_LOCK) break; udelay(1); } /* PLL enter normal-mode */ - writel(RK_CLRSETBITS(DPLL_MODE_MSK, DPLL_MODE_NORM), - &cru_ptr->cru_mode_con); + write32(&cru_ptr->cru_mode_con, + RK_CLRSETBITS(DPLL_MODE_MSK, DPLL_MODE_NORM)); } void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy) @@ -417,22 +398,16 @@ void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy) u32 phy_psrstn_shift = 1 + 5 * ch; u32 phy_srstn_shift = 5 * ch; - writel(RK_CLRSETBITS(1 << phy_ctl_srstn_shift, - phy << phy_ctl_srstn_shift) - | RK_CLRSETBITS(1 << ctl_psrstn_shift, ctl << ctl_psrstn_shift) - | RK_CLRSETBITS(1 << ctl_srstn_shift, ctl << ctl_srstn_shift) - | RK_CLRSETBITS(1 << phy_psrstn_shift, phy << phy_psrstn_shift) - | RK_CLRSETBITS(1 << phy_srstn_shift, phy << phy_srstn_shift), - &cru_ptr->cru_softrst_con[10]); + write32(&cru_ptr->cru_softrst_con[10], + RK_CLRSETBITS(1 << phy_ctl_srstn_shift, phy << phy_ctl_srstn_shift) | RK_CLRSETBITS(1 << ctl_psrstn_shift, ctl << ctl_psrstn_shift) | RK_CLRSETBITS(1 << ctl_srstn_shift, ctl << ctl_srstn_shift) | RK_CLRSETBITS(1 << phy_psrstn_shift, phy << phy_psrstn_shift) | RK_CLRSETBITS(1 << phy_srstn_shift, phy << phy_srstn_shift)); } void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n) { u32 phy_ctl_srstn_shift = 4 + 5 * ch; - writel(RK_CLRSETBITS(1 << phy_ctl_srstn_shift, - n << phy_ctl_srstn_shift), - &cru_ptr->cru_softrst_con[10]); + write32(&cru_ptr->cru_softrst_con[10], + RK_CLRSETBITS(1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift)); } void rkclk_configure_spi(unsigned int bus, unsigned int hz) @@ -443,19 +418,16 @@ void rkclk_configure_spi(unsigned int bus, unsigned int hz) switch (bus) { /*select gpll as spi src clk, and set div*/ case 0: - writel(RK_CLRSETBITS(1 << 7 | 0x1f << 0, 1 << 7 - | (src_clk_div - 1) << 0), - &cru_ptr->cru_clksel_con[25]); + write32(&cru_ptr->cru_clksel_con[25], + RK_CLRSETBITS(1 << 7 | 0x1f << 0, 1 << 7 | (src_clk_div - 1) << 0)); break; case 1: - writel(RK_CLRSETBITS(1 << 15 | 0x1f << 8, 1 << 15 - | (src_clk_div - 1) << 8), - &cru_ptr->cru_clksel_con[25]); + write32(&cru_ptr->cru_clksel_con[25], + RK_CLRSETBITS(1 << 15 | 0x1f << 8, 1 << 15 | (src_clk_div - 1) << 8)); break; case 2: - writel(RK_CLRSETBITS(1 << 7 | 0x1f << 0, 1 << 7 - | (src_clk_div - 1) << 0), - &cru_ptr->cru_clksel_con[39]); + write32(&cru_ptr->cru_clksel_con[39], + RK_CLRSETBITS(1 << 7 | 0x1f << 0, 1 << 7 | (src_clk_div - 1) << 0)); break; default: printk(BIOS_ERR, "do not support this spi bus\n"); @@ -481,16 +453,15 @@ void rkclk_configure_i2s(unsigned int hz) i2s0_outclk_sel: clk_i2s i2s0_clk_sel: divider ouput from fraction i2s0_pll_div_con: 0*/ - writel(RK_CLRSETBITS(1 << 15 | 1 << 12 | 3 << 8 | 0x7f << 0 , - 1 << 15 | 0 << 12 | 1 << 8 | 0 << 0), - &cru_ptr->cru_clksel_con[4]); + write32(&cru_ptr->cru_clksel_con[4], + RK_CLRSETBITS(1 << 15 | 1 << 12 | 3 << 8 | 0x7f << 0, 1 << 15 | 0 << 12 | 1 << 8 | 0 << 0)); /* set frac divider */ v = clk_gcd(GPLL_HZ, hz); n = (GPLL_HZ / v) & (0xffff); d = (hz / v) & (0xffff); assert(hz == GPLL_HZ / n * d); - writel(d << 16 | n, &cru_ptr->cru_clksel_con[8]); + write32(&cru_ptr->cru_clksel_con[8], d << 16 | n); } void rkclk_configure_crypto(unsigned int hz) @@ -499,8 +470,8 @@ void rkclk_configure_crypto(unsigned int hz) assert((div - 1 < 4) && (div * hz == PD_BUS_ACLK_HZ)); assert(hz <= 150*MHz); /* Suggested max in TRM. */ - writel(RK_CLRSETBITS(0x3 << 6, (div - 1) << 6), - &cru_ptr->cru_clksel_con[26]); + write32(&cru_ptr->cru_clksel_con[26], + RK_CLRSETBITS(0x3 << 6, (div - 1) << 6)); } void rkclk_configure_tsadc(unsigned int hz) @@ -510,8 +481,8 @@ void rkclk_configure_tsadc(unsigned int hz) div = src_clk / hz; assert((div - 1 < 64) && (div * hz == 32 * KHz)); - writel(RK_CLRSETBITS(0x3f << 0, (div - 1) << 0), - &cru_ptr->cru_clksel_con[2]); + write32(&cru_ptr->cru_clksel_con[2], + RK_CLRSETBITS(0x3f << 0, (div - 1) << 0)); } static int pll_para_config(u32 freq_hz, struct pll_div *div) @@ -579,12 +550,12 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div) void rkclk_configure_edp(void) { /* clk_edp_24M source: 24M */ - writel(RK_SETBITS(1 << 15), &cru_ptr->cru_clksel_con[28]); + write32(&cru_ptr->cru_clksel_con[28], RK_SETBITS(1 << 15)); /* rst edp */ - writel(RK_SETBITS(1 << 15), &cru_ptr->cru_softrst_con[6]); + write32(&cru_ptr->cru_softrst_con[6], RK_SETBITS(1 << 15)); udelay(1); - writel(RK_CLRBITS(1 << 15), &cru_ptr->cru_softrst_con[6]); + write32(&cru_ptr->cru_softrst_con[6], RK_CLRBITS(1 << 15)); } void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz) @@ -597,15 +568,13 @@ void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz) switch (vop_id) { case 0: - writel(RK_CLRSETBITS(3 << 6 | 0x1f << 0, - 0 << 6 | (div - 1) << 0), - &cru_ptr->cru_clksel_con[31]); + write32(&cru_ptr->cru_clksel_con[31], + RK_CLRSETBITS(3 << 6 | 0x1f << 0, 0 << 6 | (div - 1) << 0)); break; case 1: - writel(RK_CLRSETBITS(3 << 14 | 0x1f << 8, - 0 << 14 | (div - 1) << 8), - &cru_ptr->cru_clksel_con[31]); + write32(&cru_ptr->cru_clksel_con[31], + RK_CLRSETBITS(3 << 14 | 0x1f << 8, 0 << 14 | (div - 1) << 8)); break; } } @@ -618,34 +587,32 @@ int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz) return -1; /* npll enter slow-mode */ - writel(RK_CLRSETBITS(NPLL_MODE_MSK, NPLL_MODE_SLOW), - &cru_ptr->cru_mode_con); + write32(&cru_ptr->cru_mode_con, + RK_CLRSETBITS(NPLL_MODE_MSK, NPLL_MODE_SLOW)); rkclk_set_pll(&cru_ptr->cru_npll_con[0], &npll_config); /* waiting for pll lock */ while (1) { - if (readl(&rk3288_grf->soc_status[1]) & SOCSTS_NPLL_LOCK) + if (read32(&rk3288_grf->soc_status[1]) & SOCSTS_NPLL_LOCK) break; udelay(1); } /* npll enter normal-mode */ - writel(RK_CLRSETBITS(NPLL_MODE_MSK, NPLL_MODE_NORM), - &cru_ptr->cru_mode_con); + write32(&cru_ptr->cru_mode_con, + RK_CLRSETBITS(NPLL_MODE_MSK, NPLL_MODE_NORM)); /* vop dclk source clk: npll,dclk_div: 1 */ switch (vop_id) { case 0: - writel(RK_CLRSETBITS(0xff << 8 | 3 << 0, - 0 << 8 | 2 << 0), - &cru_ptr->cru_clksel_con[27]); + write32(&cru_ptr->cru_clksel_con[27], + RK_CLRSETBITS(0xff << 8 | 3 << 0, 0 << 8 | 2 << 0)); break; case 1: - writel(RK_CLRSETBITS(0xff << 8 | 3 << 6, - 0 << 8 | 2 << 6), - &cru_ptr->cru_clksel_con[29]); + write32(&cru_ptr->cru_clksel_con[29], + RK_CLRSETBITS(0xff << 8 | 3 << 6, 0 << 8 | 2 << 6)); break; } return 0; @@ -654,5 +621,5 @@ int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz) int rkclk_was_watchdog_reset(void) { /* Bits 5 and 4 are "second" and "first" global watchdog reset. */ - return readl(&cru_ptr->cru_glb_rst_st) & 0x30; + return read32(&cru_ptr->cru_glb_rst_st) & 0x30; } |