diff options
Diffstat (limited to 'src/soc/rockchip/common/edp.c')
| -rw-r--r-- | src/soc/rockchip/common/edp.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/src/soc/rockchip/common/edp.c b/src/soc/rockchip/common/edp.c index ea0930a058..18afc3a50a 100644 --- a/src/soc/rockchip/common/edp.c +++ b/src/soc/rockchip/common/edp.c @@ -97,7 +97,7 @@ static void rk_edp_init_interrupt(struct rk_edp *edp) static void rk_edp_enable_sw_function(struct rk_edp *edp) { - clrbits_le32(&edp->regs->func_en_1, SW_FUNC_EN_N); + clrbits32(&edp->regs->func_en_1, SW_FUNC_EN_N); } static int rk_edp_get_pll_lock_status(struct rk_edp *edp) @@ -116,7 +116,7 @@ static void rk_edp_init_analog_func(struct rk_edp *edp) write32(&edp->regs->common_int_sta_1, PLL_LOCK_CHG); - clrbits_le32(&edp->regs->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL); + clrbits32(&edp->regs->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL); stopwatch_init_msecs_expire(&sw, PLL_LOCK_TIMEOUT); @@ -128,7 +128,7 @@ static void rk_edp_init_analog_func(struct rk_edp *edp) } /* Enable Serdes FIFO function and Link symbol clock domain module */ - clrbits_le32(&edp->regs->func_en_2, SERDES_FIFO_FUNC_EN_N | + clrbits32(&edp->regs->func_en_2, SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N | SSC_FUNC_EN_N); } @@ -139,20 +139,20 @@ static void rk_edp_init_aux(struct rk_edp *edp) write32(&edp->regs->dp_int_sta, AUX_FUNC_EN_N); /* Disable AUX channel module */ - setbits_le32(&edp->regs->func_en_2, AUX_FUNC_EN_N); + setbits32(&edp->regs->func_en_2, AUX_FUNC_EN_N); /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ write32(&edp->regs->aux_ch_defer_dtl, DEFER_CTRL_EN | DEFER_COUNT(1)); /* Enable AUX channel module */ - clrbits_le32(&edp->regs->func_en_2, AUX_FUNC_EN_N); + clrbits32(&edp->regs->func_en_2, AUX_FUNC_EN_N); } static int rk_edp_aux_enable(struct rk_edp *edp) { struct stopwatch sw; - setbits_le32(&edp->regs->aux_ch_ctl_2, AUX_EN); + setbits32(&edp->regs->aux_ch_ctl_2, AUX_EN); stopwatch_init_msecs_expire(&sw, 20); do { if (!(read32(&edp->regs->aux_ch_ctl_2) & AUX_EN)) @@ -698,7 +698,7 @@ static int rk_edp_read_bytes_from_i2c(struct rk_edp *edp, write32(&edp->regs->buf_data_ctl, val); /* Set normal AUX CH command */ - clrbits_le32(&edp->regs->aux_ch_ctl_2, ADDR_ONLY); + clrbits32(&edp->regs->aux_ch_ctl_2, ADDR_ONLY); /* * If Rx sends defer, Tx sends only reads @@ -816,7 +816,7 @@ static void rk_edp_init_video(struct rk_edp *edp) static void rk_edp_config_video_slave_mode(struct rk_edp *edp) { - clrbits_le32(&edp->regs->func_en_1, + clrbits32(&edp->regs->func_en_1, VID_FIFO_FUNC_EN_N | VID_CAP_FUNC_EN_N); } @@ -828,7 +828,7 @@ static void rk_edp_set_video_cr_mn(struct rk_edp *edp, u32 val; if (type == REGISTER_M) { - setbits_le32(&edp->regs->sys_ctl_4, FIX_M_VID); + setbits32(&edp->regs->sys_ctl_4, FIX_M_VID); val = m_value & 0xff; write32(&edp->regs->m_vid_0, val); val = (m_value >> 8) & 0xff; @@ -843,7 +843,7 @@ static void rk_edp_set_video_cr_mn(struct rk_edp *edp, val = (n_value >> 16) & 0xff; write32(&edp->regs->n_vid_2, val); } else { - clrbits_le32(&edp->regs->sys_ctl_4, FIX_M_VID); + clrbits32(&edp->regs->sys_ctl_4, FIX_M_VID); write32(&edp->regs->n_vid_0, 0x00); write32(&edp->regs->n_vid_1, 0x80); @@ -914,10 +914,10 @@ static int rk_edp_config_video(struct rk_edp *edp) rk_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0); /* For video bist, Video timing must be generated by register */ - clrbits_le32(&edp->regs->video_ctl_10, F_SEL); + clrbits32(&edp->regs->video_ctl_10, F_SEL); /* Disable video mute */ - clrbits_le32(&edp->regs->video_ctl_1, VIDEO_MUTE); + clrbits32(&edp->regs->video_ctl_1, VIDEO_MUTE); return 0; } @@ -1000,7 +1000,7 @@ int rk_edp_prepare(void) int rk_edp_enable(void) { /* Enable video at next frame */ - setbits_le32(&rk_edp.regs->video_ctl_1, VIDEO_EN); + setbits32(&rk_edp.regs->video_ctl_1, VIDEO_EN); return rk_edp_is_video_stream_on(&rk_edp); } |