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-rw-r--r--src/soc/rdc/r8610/Kconfig28
-rw-r--r--src/soc/rdc/r8610/Makefile.inc23
-rw-r--r--src/soc/rdc/r8610/bootblock.c26
-rw-r--r--src/soc/rdc/r8610/northbridge.c124
-rw-r--r--src/soc/rdc/r8610/r8610.c116
5 files changed, 317 insertions, 0 deletions
diff --git a/src/soc/rdc/r8610/Kconfig b/src/soc/rdc/r8610/Kconfig
new file mode 100644
index 0000000000..d849f9c9d2
--- /dev/null
+++ b/src/soc/rdc/r8610/Kconfig
@@ -0,0 +1,28 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008-2009 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config SOC_RDC_R8610
+ bool
+ select ARCH_BOOTBLOCK_X86_32
+ select ARCH_VERSTAGE_X86_32
+ select ARCH_ROMSTAGE_X86_32
+ select ARCH_RAMSTAGE_X86_32
+ select ROMCC
+ select LATE_CBMEM_INIT
+
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+ string
+ default "soc/rdc/r8610/bootblock.c"
+ depends on SOC_RDC_R8610
diff --git a/src/soc/rdc/r8610/Makefile.inc b/src/soc/rdc/r8610/Makefile.inc
new file mode 100644
index 0000000000..652562cb96
--- /dev/null
+++ b/src/soc/rdc/r8610/Makefile.inc
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
+## Copyright (C) 2007, 2009 Rudolf Marek <r.marek@assembler.cz>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+ifeq ($(CONFIG_SOC_RDC_R8610),y)
+
+ramstage-y += northbridge.c
+ramstage-y += r8610.c
+
+endif
diff --git a/src/soc/rdc/r8610/bootblock.c b/src/soc/rdc/r8610/bootblock.c
new file mode 100644
index 0000000000..0dc776ea93
--- /dev/null
+++ b/src/soc/rdc/r8610/bootblock.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <device/pci_def.h>
+
+static void bootblock_southbridge_init(void)
+{
+ uint32_t tmp;
+
+ tmp = pci_read_config32(PCI_DEV(0, 7, 0), 0x40);
+ /* decode all flash ranges */
+ pci_write_config32(PCI_DEV(0, 7, 0), 0x40, tmp | 0x07ff0000);
+}
diff --git a/src/soc/rdc/r8610/northbridge.c b/src/soc/rdc/r8610/northbridge.c
new file mode 100644
index 0000000000..00aa0d419a
--- /dev/null
+++ b/src/soc/rdc/r8610/northbridge.c
@@ -0,0 +1,124 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * Based on qemu-x86/northbridge.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <stdlib.h>
+#include <string.h>
+#include <smbios.h>
+#include <cbmem.h>
+
+static unsigned long get_memory_size(void)
+{
+ device_t nb_dev;
+ u8 size;
+
+ nb_dev = dev_find_device(PCI_VENDOR_ID_RDC,
+ PCI_DEVICE_ID_RDC_R8610_NB, 0);
+ size = pci_read_config8(nb_dev, 0x6d) & 0xf;
+ return (2 * 1024) << size;
+}
+
+static void cpu_pci_domain_set_resources(device_t dev)
+{
+ u32 pci_tolm = find_pci_tolm(dev->link_list);
+ unsigned long tomk = 0, tolmk;
+ int idx;
+
+ tomk = get_memory_size();
+ printk(BIOS_DEBUG, "Detected %lu Kbytes (%lu MiB) RAM.\n",
+ tomk, tomk / 1024);
+
+ /* Compute the top of Low memory */
+ tolmk = pci_tolm >> 10;
+ if (tolmk >= tomk) {
+ /* The PCI hole does not overlap the memory. */
+ tolmk = tomk;
+ }
+
+ /* Report the memory regions. */
+ idx = 10;
+ ram_resource(dev, idx++, 0, 640);
+ ram_resource(dev, idx++, 768, tolmk - 768);
+
+ set_top_of_ram(tomk * 1024);
+
+ assign_resources(dev->link_list);
+}
+
+static void cpu_pci_domain_read_resources(struct device *dev)
+{
+ pci_domain_read_resources(dev);
+}
+
+#if CONFIG_GENERATE_SMBIOS_TABLES
+static int rdc_get_smbios_data16(int handle, unsigned long *current)
+{
+ struct smbios_type16 *t = (struct smbios_type16 *)*current;
+ int len = sizeof(struct smbios_type16);
+
+ memset(t, 0, sizeof(struct smbios_type16));
+ t->type = SMBIOS_PHYS_MEMORY_ARRAY;
+ t->handle = handle;
+ t->length = len - 2;
+ t->location = 3; /* Location: System Board */
+ t->use = 3; /* System memory */
+ t->memory_error_correction = 3; /* No error correction */
+ t->maximum_capacity = get_memory_size();
+ *current += len;
+ return len;
+}
+
+static int rdc_get_smbios_data(device_t dev, int *handle,
+ unsigned long *current)
+{
+ int len;
+
+ len = rdc_get_smbios_data16(*handle, current);
+ *handle += 1;
+ return len;
+}
+#endif
+static struct device_operations pci_domain_ops = {
+ .read_resources = cpu_pci_domain_read_resources,
+ .set_resources = cpu_pci_domain_set_resources,
+ .enable_resources = NULL,
+ .init = NULL,
+ .scan_bus = pci_domain_scan_bus,
+ .ops_pci_bus = pci_bus_default_ops,
+#if CONFIG_GENERATE_SMBIOS_TABLES
+ .get_smbios_data = rdc_get_smbios_data,
+#endif
+};
+
+static void enable_dev(struct device *dev)
+{
+ if (dev->path.type == DEVICE_PATH_DOMAIN) {
+ /* Set the operations if it is a special bus type */
+ dev->ops = &pci_domain_ops;
+ }
+}
+
+struct chip_operations northbridge_rdc_r8610_ops = {
+ CHIP_NAME("RDC R8610 Northbridge")
+ .enable_dev = enable_dev,
+};
diff --git a/src/soc/rdc/r8610/r8610.c b/src/soc/rdc/r8610/r8610.c
new file mode 100644
index 0000000000..e34a29940e
--- /dev/null
+++ b/src/soc/rdc/r8610/r8610.c
@@ -0,0 +1,116 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <pc80/i8259.h>
+#include <stdlib.h>
+
+static const unsigned char enetIrqs[4] = { 10, 0, 0, 0 };
+static const unsigned char usbIrqs[4] = { 15, 14, 0, 0 };
+
+static void pci_routing_fixup(struct device *dev)
+{
+ pci_assign_irqs(0, 0x8, enetIrqs);
+ pci_assign_irqs(0, 0xa, usbIrqs);
+}
+
+static void r8610_init(struct device *dev)
+{
+ device_t nb_dev;
+ u32 tmp;
+
+ printk(BIOS_DEBUG, "r8610 init\n");
+
+ /* clear DMA? */
+ outb(0x4, 0x8);
+ outb(0x4, 0x10);
+
+ outb(0xfc, 0x61);
+
+ /* Set serial base */
+ pci_write_config32(dev, 0x54, 0x3f8);
+ /* serial IRQ disable, LPC disable,
+ * COM2 goes to LPC, internal UART for COM1
+ */
+ pci_write_config32(dev, 0x50, 0x84101012);
+
+ /* Enable internal Port92, enable chipselect for flash */
+ tmp = pci_read_config32(dev, 0x40);
+ pci_write_config32(dev, 0x40, tmp | 0x07FF0600);
+
+ /* buffer strength SB pins */
+ pci_write_config32(dev, 0x5c, 0x2315);
+
+ /* EHCI 14, OHCI 15, MAC1 disable, MAC0 10, INTD 9,
+ * INTC 9, INTB 12, INTA INT10
+ */
+ pci_write_config32(dev, 0x58, 0xdf0311b3);
+
+ /* USB PHY control */
+ nb_dev = dev_find_device(PCI_VENDOR_ID_RDC,
+ PCI_DEVICE_ID_RDC_R8610_NB, 0);
+
+ tmp = pci_read_config32(nb_dev, 0xc0);
+ tmp |= 0x40000;
+ pci_write_config32(nb_dev, 0xc0, tmp);
+
+ setup_i8259();
+}
+
+static void r8610_read_resources(device_t dev)
+{
+ struct resource *res;
+
+ pci_dev_read_resources(dev);
+
+ res = new_resource(dev, 1);
+ res->base = 0x0UL;
+ res->size = 0x1000UL;
+ res->limit = 0xffffUL;
+ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+ /* Reserve space for flash */
+ res = new_resource(dev, 2);
+ res->base = 0xff800000;
+ res->size = 8*1024*1024;
+ res->limit = 0xffffffffUL;
+ res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
+ IORESOURCE_ASSIGNED;
+}
+
+static void southbridge_init(struct device *dev)
+{
+ r8610_init(dev);
+ pci_routing_fixup(dev);
+}
+
+static struct device_operations r8610_sb_ops = {
+ .read_resources = r8610_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = &southbridge_init,
+ .enable = 0,
+ .ops_pci = 0,
+};
+
+static const struct pci_driver lpc_driver __pci_driver = {
+ .ops = &r8610_sb_ops,
+ .vendor = PCI_VENDOR_ID_RDC,
+ .device = PCI_DEVICE_ID_RDC_R8610_SB,
+};
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 20:46:18 +0000