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-rw-r--r--src/soc/qualcomm/ipq806x/Kconfig8
-rw-r--r--src/soc/qualcomm/ipq806x/Makefile.inc21
2 files changed, 21 insertions, 8 deletions
diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig
index 0f65990385..88dbd36431 100644
--- a/src/soc/qualcomm/ipq806x/Kconfig
+++ b/src/soc/qualcomm/ipq806x/Kconfig
@@ -13,11 +13,11 @@ config BOOTBLOCK_ROM_OFFSET
config CBFS_HEADER_ROM_OFFSET
hex "offset of master CBFS header in ROM"
- default 0x18000
+ default 0x221000
config CBFS_ROM_OFFSET
hex "offset of CBFS data in ROM"
- default 0x18080
+ default 0x221080
config MBN_ENCAPSULATION
depends on USE_BLOBS
@@ -34,7 +34,7 @@ config SBL_BLOB
vendor.
config BOOTBLOCK_BASE
- hex "64K bytes left for TZBSP"
- default 0x2a010000
+ hex "256K bytes left for TZBSP"
+ default 0x2a040000
endif
diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc
index 2487f46ab2..1da8489eda 100644
--- a/src/soc/qualcomm/ipq806x/Makefile.inc
+++ b/src/soc/qualcomm/ipq806x/Makefile.inc
@@ -7,12 +7,25 @@ romstage-y += timer.c
ramstage-y += cbfs.c
ramstage-y += timer.c
-ifeq ($(CONFIG_MBN_ENCAPSULATION),y)
+ifeq ($(CONFIG_USE_BLOBS),y)
-$(objcbfs)/%.bin: $(objcbfs)/%.elf
+# Generate the actual coreboot bootblock code
+$(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf
@printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
- $(OBJCOPY_bootblock) -O binary $< $@.prembn
+ $(OBJCOPY_bootblock) -O binary $< $@.tmp
+ @mv $@.tmp $@
+
+# Add MBN header to allow SBL3 to start coreboot bootblock
+$(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw
@printf " ADD MBN $(subst $(obj)/,,$(@))\n"
- ./util/ipqheader/ipqheader.py $(CONFIG_BOOTBLOCK_BASE) $@.prembn $@.tmp
+ ./util/ipqheader/ipqheader.py $(CONFIG_BOOTBLOCK_BASE) $< $@.tmp
@mv $@.tmp $@
+
+# Create a complete bootblock which will start up the system
+$(objcbfs)/bootblock.bin: ./$(call strip_quotes,$(CONFIG_SBL_BLOB)) \
+ $(objcbfs)/bootblock.mbn
+ @printf " CAT $(subst $(obj)/,,$(@))\n"
+ @cat $^ > $@.tmp
+ @mv $@.tmp $@
+
endif