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-rw-r--r--src/soc/qualcomm/qcs405/clock.c101
-rw-r--r--src/soc/qualcomm/qcs405/include/soc/clock.h43
2 files changed, 109 insertions, 35 deletions
diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c
index 369bcdf531..ebad13b721 100644
--- a/src/soc/qualcomm/qcs405/clock.c
+++ b/src/soc/qualcomm/qcs405/clock.c
@@ -209,11 +209,38 @@ void clock_configure_uart(uint32_t hz)
clock_configure(uart_clk, uart_cfg, hz, ARRAY_SIZE(uart_cfg));
}
-void clock_configure_spi(int blsp, uint32_t hz)
+void clock_configure_spi(int blsp, int qup, uint32_t hz)
{
- struct qcs405_clock *spi_clk = (blsp == 1) ?
- (struct qcs405_clock *)&gcc->blsp1_qup4_spi_clk
- : (struct qcs405_clock *)&gcc->blsp2_qup0_spi_clk;
+ struct qcs405_clock *spi_clk = 0;
+
+ if (blsp == 1) {
+ switch (qup) {
+ case 0:
+ spi_clk = (struct qcs405_clock *)
+ &gcc->blsp1_qup0_spi_clk;
+ break;
+ case 1:
+ spi_clk = (struct qcs405_clock *)
+ &gcc->blsp1_qup1_spi_clk;
+ break;
+ case 2:
+ spi_clk = (struct qcs405_clock *)
+ &gcc->blsp1_qup2_spi_clk;
+ break;
+ case 3:
+ spi_clk = (struct qcs405_clock *)
+ &gcc->blsp1_qup3_spi_clk;
+ break;
+ case 4:
+ spi_clk = (struct qcs405_clock *)
+ &gcc->blsp1_qup4_spi_clk;
+ break;
+ }
+ } else if (blsp == 2)
+ spi_clk = (struct qcs405_clock *)&gcc->blsp2_qup0_spi_clk;
+
+ else
+ printk(BIOS_ERR, "BLSP%d not supported\n", blsp);
clock_configure(spi_clk, spi_cfg, hz, ARRAY_SIZE(spi_cfg));
}
@@ -228,38 +255,66 @@ void clock_disable_uart(void)
clock_disable(&gcc->blsp1_uart2_apps_cbcr);
}
-void clock_enable_spi(int blsp)
+void clock_enable_spi(int blsp, int qup)
{
- (blsp == 1) ? clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr)
- : clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr);
+ if (blsp == 1) {
+ switch (qup) {
+ case 0:
+ clock_enable(&gcc->blsp1_qup0_spi_apps_cbcr);
+ break;
+ case 1:
+ clock_enable(&gcc->blsp1_qup1_spi_apps_cbcr);
+ break;
+ case 2:
+ clock_enable(&gcc->blsp1_qup2_spi_apps_cbcr);
+ break;
+ case 3:
+ clock_enable(&gcc->blsp1_qup3_spi_apps_cbcr);
+ break;
+ case 4:
+ clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr);
+ break;
+ }
+ } else if (blsp == 2)
+ clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr);
+ else
+ printk(BIOS_ERR, "BLSP%d not supported\n", blsp);
}
-void clock_disable_spi(int blsp)
+void clock_disable_spi(int blsp, int qup)
{
- (blsp == 1) ? clock_disable(&gcc->blsp1_qup4_spi_apps_cbcr)
- : clock_disable(&gcc->blsp2_qup0_spi_apps_cbcr);
+ if (blsp == 1) {
+ switch (qup) {
+ case 0:
+ clock_enable(&gcc->blsp1_qup0_spi_apps_cbcr);
+ break;
+ case 1:
+ clock_enable(&gcc->blsp1_qup1_spi_apps_cbcr);
+ break;
+ case 2:
+ clock_enable(&gcc->blsp1_qup2_spi_apps_cbcr);
+ break;
+ case 3:
+ clock_enable(&gcc->blsp1_qup3_spi_apps_cbcr);
+ break;
+ case 4:
+ clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr);
+ break;
+ }
+ } else if (blsp == 2)
+ clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr);
+ else
+ printk(BIOS_ERR, "BLSP%d not supported\n", blsp);
+
}
void clock_init(void)
{
-
clock_configure_gpll0();
-
- clock_configure(&gcc->blsp1_uart2_apps_clk, uart_cfg, 1843200,
- ARRAY_SIZE(uart_cfg));
-
- clock_enable(&gcc->blsp1_uart2_apps_cbcr);
clock_enable_vote(&gcc->blsp1_ahb_cbcr,
&gcc->gcc_apcs_clock_branch_en_vote,
BLSP1_AHB_CLK_ENA);
- clock_configure(&gcc->blsp1_qup4_spi_clk, spi_cfg, 1000000,
- ARRAY_SIZE(spi_cfg));
- clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr);
-
- clock_configure(&gcc->blsp2_qup0_spi_clk, spi_cfg, 50000000,
- ARRAY_SIZE(spi_cfg));
- clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr);
clock_enable_vote(&gcc->blsp2_ahb_cbcr,
&gcc->gcc_apcs_clock_branch_en_vote,
BLSP2_AHB_CLK_ENA);
diff --git a/src/soc/qualcomm/qcs405/include/soc/clock.h b/src/soc/qualcomm/qcs405/include/soc/clock.h
index d0f307b308..8638128b15 100644
--- a/src/soc/qualcomm/qcs405/include/soc/clock.h
+++ b/src/soc/qualcomm/qcs405/include/soc/clock.h
@@ -21,7 +21,6 @@
#define BLSP2_AHB_CLK_ENA 20
#define SRC_XO_19_2MHZ 0
#define SRC_GPLL0_MAIN_800MHZ 1
-#define REG(addr) ((void *)addr)
/**
* USB BCR registers
@@ -66,28 +65,48 @@ struct qcs405_gcc {
u32 blsp1_bcr;
u32 blsp1_sleep_cbcr;
u32 blsp1_ahb_cbcr;
- u8 _res1[0x3028 - 0x100c];
+ struct qcs405_rcg gcc_blsp_uart_sim_rcg;
+ u8 _res1[0x2000 - 0x1014];
+ u32 blsp1_qup1_bcr;
+ u32 blsp1_qup1_spi_apps_cbcr;
+ u8 _res2[0x2024 - 0x2008];
+ struct qcs405_clock blsp1_qup1_spi_clk;
+ u8 _res3[0x3008-0x2038];
+ u32 blsp1_qup2_bcr;
+ u32 blsp1_qup2_spi_apps_cbcr;
+ u8 _res4[0x3014 - 0x3010];
+ struct qcs405_clock blsp1_qup2_spi_clk;
u32 blsp1_uart2_bcr;
u32 blsp1_uart2_apps_cbcr;
u32 blsp1_uart2_sim_cbcr;
struct qcs405_clock blsp1_uart2_apps_clk;
- u8 _res2[0x5018 - 0x3048];
+ u8 _res5[0x4018 - 0x3048];
+ u32 blsp1_qup3_bcr;
+ u32 blsp1_qup3_spi_apps_cbcr;
+ u8 _res6[0x4024 - 0x4020];
+ struct qcs405_clock blsp1_qup3_spi_clk;
+ u8 _res7[0x5018 - 0x4038];
u32 blsp1_qup4_bcr;
u32 blsp1_qup4_spi_apps_cbcr;
- u8 _res3[0x5024 - 0x5020];
+ u8 _res8[0x5024 - 0x5020];
struct qcs405_clock blsp1_qup4_spi_clk;
- u8 _res4[0xB000 - 0x5038];
+ u8 _res9[0x6020 - 0x5038];
+ u32 blsp1_qup0_bcr;
+ u32 blsp1_qup0_spi_apps_cbcr;
+ u8 _res10[0x6034 - 0x6028];
+ struct qcs405_clock blsp1_qup0_spi_clk;
+ u8 _res11[0xB000 - 0x6048];
u32 blsp2_bcr;
u32 blsp2_sleep_cbcr;
u32 blsp2_ahb_cbcr;
- u8 _res5[0xC000 - 0xB00C];
+ u8 _res12[0xC000 - 0xB00C];
u32 blsp2_qup0_bcr;
u32 blsp2_qup0_spi_apps_cbcr;
- u8 _res6[0xC024 - 0xC008];
+ u8 _res13[0xC024 - 0xC008];
struct qcs405_clock blsp2_qup0_spi_clk;
- u8 _res7[0x21000 - 0xC038];
+ u8 _res14[0x21000 - 0xC038];
struct qcs405_gpll gpll0;
- u8 _res8[0x45004 - 0x21024];
+ u8 _res15[0x45004 - 0x21024];
u32 gcc_apcs_clock_branch_en_vote;
};
@@ -160,10 +179,10 @@ void clock_reset_aop(void);
int clock_configure_qspi(uint32_t hz);
int clock_reset_bcr(void *bcr_addr, bool reset);
void clock_configure_uart(uint32_t hz);
-void clock_configure_spi(int blsp, uint32_t hz);
+void clock_configure_spi(int blsp, int qup, uint32_t hz);
void clock_enable_uart(void);
void clock_disable_uart(void);
-void clock_enable_spi(int blsp);
-void clock_disable_spi(int blsp);
+void clock_enable_spi(int blsp, int qup);
+void clock_disable_spi(int blsp, int qup);
#endif // __SOC_QUALCOMM_QCS405_CLOCK_H__
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 11:52:34 +0000