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-rw-r--r--src/soc/nvidia/tegra132/bootblock.c6
-rw-r--r--src/soc/nvidia/tegra132/clock.c7
2 files changed, 5 insertions, 8 deletions
diff --git a/src/soc/nvidia/tegra132/bootblock.c b/src/soc/nvidia/tegra132/bootblock.c
index f377bc1ee0..46b7b3ab56 100644
--- a/src/soc/nvidia/tegra132/bootblock.c
+++ b/src/soc/nvidia/tegra132/bootblock.c
@@ -54,12 +54,16 @@ void main(void)
if (CONFIG_BOOTBLOCK_CONSOLE) {
console_init();
exception_init();
- printk(BIOS_INFO, "Tegra132: Bootblock here\n");
+ printk(BIOS_INFO, "T132: Bootblock here\n");
}
clock_init();
+ printk(BIOS_INFO, "T132 bootblock: Clock init done\n");
+
bootblock_mainboard_init();
+ printk(BIOS_INFO, "T132 bootblock: Mainboard bootblock init done\n");
+
while(1);
}
diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c
index 9db957c9fa..66eaf1e51a 100644
--- a/src/soc/nvidia/tegra132/clock.c
+++ b/src/soc/nvidia/tegra132/clock.c
@@ -519,9 +519,6 @@ void clock_init(void)
clrsetbits_le32(&pmc->osc_edpd_over, PMC_OSC_EDPD_OVER_XOFS_MASK,
OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT);
- /* Disable IDDQ for PLLX before we set it up (from U-Boot -- why?) */
- clrbits_le32(&clk_rst->pllx_misc3, PLLX_IDDQ_MASK);
-
/* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */
write32((CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT |
PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT |
@@ -534,10 +531,6 @@ void clock_init(void)
PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT,
&clk_rst->pllp_outb);
- /* init pllx */
- init_pll(&clk_rst->pllx_base, &clk_rst->pllx_misc,
- osc_table[osc].pllx, PLLPAXS_MISC_LOCK_ENABLE);
-
/* init pllu */
init_pll(&clk_rst->pllu_base, &clk_rst->pllu_misc,
osc_table[osc].pllu, PLLUD_MISC_LOCK_ENABLE);