diff options
Diffstat (limited to 'src/soc/nvidia/tegra210')
| -rw-r--r-- | src/soc/nvidia/tegra210/include/soc/clk_rst.h | 14 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/include/soc/tegra_dsi.h | 2 |
2 files changed, 8 insertions, 8 deletions
diff --git a/src/soc/nvidia/tegra210/include/soc/clk_rst.h b/src/soc/nvidia/tegra210/include/soc/clk_rst.h index 781a4e2482..652bcaaf27 100644 --- a/src/soc/nvidia/tegra210/include/soc/clk_rst.h +++ b/src/soc/nvidia/tegra210/include/soc/clk_rst.h @@ -416,7 +416,7 @@ enum { #define PLLM_MISC2_KCP_SHIFT 1 #define PLLM_MISC2_KVCO_SHIFT 0 #define PLLM_OUT1_RSTN_RESET_DISABLE (1 << 0) -#define PLLM_EN_LCKDET (1 << 4) +#define PLLM_EN_LCKDET (1 << 4) /* PLLU specific registers */ #define PLLU_MISC_IDDQ (1U << 31) @@ -527,12 +527,12 @@ enum { #define SCLK_DIVISOR_MASK (0xff << SCLK_DIVISOR_SHIFT) /* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */ -#define HCLK_DISABLE (1 << 7) -#define HCLK_DIVISOR_SHIFT 4 -#define HCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT) -#define PCLK_DISABLE (1 << 3) -#define PCLK_DIVISOR_SHIFT 0 -#define PCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT) +#define HCLK_DISABLE (1 << 7) +#define HCLK_DIVISOR_SHIFT 4 +#define HCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT) +#define PCLK_DISABLE (1 << 3) +#define PCLK_DIVISOR_SHIFT 0 +#define PCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT) /* CPU_SOFTRST_CTRL2_0 0x388 */ #define CAR2PMC_CPU_ACK_WIDTH_MASK 0xfff diff --git a/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h b/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h index 4b4f14e01d..dbaaa2233c 100644 --- a/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h +++ b/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h @@ -149,7 +149,7 @@ #define PKT_LP (1 << 30) #define NUM_PKT_SEQ 12 -#define APB_MISC_GP_MIPI_PAD_CTRL_0 (TEGRA_APB_MISC_GP_BASE + 0x20) +#define APB_MISC_GP_MIPI_PAD_CTRL_0 (TEGRA_APB_MISC_GP_BASE + 0x20) #define DSIB_MODE_SHIFT 1 #define DSIB_MODE_CSI (0 << DSIB_MODE_SHIFT) #define DSIB_MODE_DSI (1 << DSIB_MODE_SHIFT) |