diff options
Diffstat (limited to 'src/soc/nvidia/tegra210')
| -rw-r--r-- | src/soc/nvidia/tegra210/Kconfig | 10 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/cpu.c | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/include/soc/memlayout.ld | 7 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld | 9 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/maincpu.S | 55 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/ramstage.c | 17 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/romstage.c | 5 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/stage_entry.S | 12 |
8 files changed, 40 insertions, 77 deletions
diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index 002a6d3806..5273d81782 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -6,7 +6,6 @@ config SOC_NVIDIA_TEGRA210 select ARCH_VERSTAGE_ARMV4 select ARCH_ROMSTAGE_ARMV4 select ARCH_RAMSTAGE_ARMV8_64 - select ARCH_ARM64_CPU_CORTEX_A57 select BOOTBLOCK_CONSOLE select GIC select HAVE_MONOTONIC_TIMER @@ -22,11 +21,6 @@ if SOC_NVIDIA_TEGRA210 config CHROMEOS select CHROMEOS_RAMOOPS_NON_ACPI -# TODO: Remove after replacing arch/arm64/stage_entry.S -config STACK_SIZE - hex - default 0x1000 - config MAINBOARD_DO_DSI_INIT bool "Use dsi graphics interface" depends on MAINBOARD_DO_NATIVE_VGA_INIT @@ -41,10 +35,6 @@ config MAINBOARD_DO_SOR_INIT help Initialize dp display -config MAX_CPUS - int - default 4 - choice CONSOLE_SERIAL_TEGRA210_UART_CHOICES prompt "Serial Console UART" default CONSOLE_SERIAL_TEGRA210_UARTA diff --git a/src/soc/nvidia/tegra210/cpu.c b/src/soc/nvidia/tegra210/cpu.c index a837a99cc0..0303150ac6 100644 --- a/src/soc/nvidia/tegra210/cpu.c +++ b/src/soc/nvidia/tegra210/cpu.c @@ -23,7 +23,7 @@ static void enable_core_clocks(int cpu) { - const uint32_t cpu_clocks[CONFIG_MAX_CPUS] = { + const uint32_t cpu_clocks[] = { [0] = CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CX0, [1] = CRC_RST_CPUG_CLR_CPU1 | CRC_RST_CPUG_CLR_DBG1 | diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld index 0338cd9604..00ecd28224 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld @@ -14,6 +14,7 @@ */ #include <memlayout.h> +#include <rules.h> #include <arch/header.ld> @@ -29,7 +30,11 @@ SECTIONS SRAM_START(0x40000000) PRERAM_CBMEM_CONSOLE(0x40000000, 8K) PRERAM_CBFS_CACHE(0x40002000, 84K) - STACK(0x40017000, 16K) +#if ENV_ARM64 + STACK(0x40017000, 8K) +#else /* AVP gets a separate stack to avoid any chance of handoff races. */ + STACK(0x40019000, 8K) +#endif TIMESTAMP(0x4001B000, 2K) BOOTBLOCK(0x4001B800, 24K) ROMSTAGE(0x40022000, 120K) diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld index b4b3dc2822..c1c581bf71 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld @@ -14,6 +14,7 @@ */ #include <memlayout.h> +#include <rules.h> #include <arch/header.ld> @@ -29,8 +30,12 @@ SECTIONS SRAM_START(0x40000000) PRERAM_CBMEM_CONSOLE(0x40000000, 8K) PRERAM_CBFS_CACHE(0x40002000, 36K) - VBOOT2_WORK(0x4000B000, 16K) - STACK(0x4000F000, 2K) + VBOOT2_WORK(0x4000B000, 12K) +#if ENV_ARM64 + STACK(0x4000E000, 3K) +#else /* AVP gets a separate stack to avoid any chance of handoff races. */ + STACK(0x4000EC00, 3K) +#endif TIMESTAMP(0x4000F800, 2K) BOOTBLOCK(0x40010000, 28K) VERSTAGE(0x40017000, 64K) diff --git a/src/soc/nvidia/tegra210/maincpu.S b/src/soc/nvidia/tegra210/maincpu.S deleted file mode 100644 index 898d821d7e..0000000000 --- a/src/soc/nvidia/tegra210/maincpu.S +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include <arch/asm.h> - -ENTRY(maincpu_setup) - /* - * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data - * aborts may happen early and crash before the abort handlers are - * installed, but at least the problem will show up near the code that - * causes it. - */ - msr cpsr, #0xdf - - ldr sp, maincpu_stack_pointer - eor lr, lr - ldr r0, maincpu_entry_point - bx r0 -ENDPROC(maincpu_setup) - - .align 2 - - .global maincpu_stack_pointer -maincpu_stack_pointer: - .word 0 - - .global maincpu_entry_point -maincpu_entry_point: - .word 0 diff --git a/src/soc/nvidia/tegra210/ramstage.c b/src/soc/nvidia/tegra210/ramstage.c index 5c375106a2..18fdded800 100644 --- a/src/soc/nvidia/tegra210/ramstage.c +++ b/src/soc/nvidia/tegra210/ramstage.c @@ -16,12 +16,13 @@ #include <arch/clock.h> #include <arch/cpu.h> #include <arch/stages.h> +#include <gic.h> #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/mmu_operations.h> #include <soc/mtc.h> -void arm64_arch_timer_init(void) +static void arm64_arch_timer_init(void) { uint32_t freq = clock_get_osc_khz() * 1000; // Set the cntfrq register. @@ -47,11 +48,20 @@ static void mselect_enable_wrap(void) write32((void *)TEGRA_MSELECT_CONFIG, reg); } -void arm64_soc_init(void) +/* Tegra-specific entry point, called from assembly in stage_entry.S */ +void ramstage_entry(void); +void ramstage_entry(void) { + /* TODO: Is this still needed? */ + gic_init(); + + /* TODO: Move arch timer setup to BL31? */ + arm64_arch_timer_init(); + /* Enable WRAP to INCR burst type conversion in MSELECT */ mselect_enable_wrap(); + /* TODO: Move TrustZone setup to BL31? */ trustzone_region_init(); tegra210_mmu_init(); @@ -60,4 +70,7 @@ void arm64_soc_init(void) if (tegra210_run_mtc() != 0) printk(BIOS_ERR, "MTC: No training data.\n"); + + /* Jump to boot state machine in common code. */ + main(); } diff --git a/src/soc/nvidia/tegra210/romstage.c b/src/soc/nvidia/tegra210/romstage.c index 23c526613c..c9ff35bfb5 100644 --- a/src/soc/nvidia/tegra210/romstage.c +++ b/src/soc/nvidia/tegra210/romstage.c @@ -19,6 +19,7 @@ #include <cbmem.h> #include <console/cbmem_console.h> #include <console/console.h> +#include <lib.h> #include <program_loading.h> #include <soc/addressmap.h> #include <soc/ccplex.h> @@ -27,6 +28,7 @@ #include <soc/sdram_configs.h> #include <soc/romstage.h> #include <soc/nvidia/tegra/apbmisc.h> +#include <symbols.h> #include <timer.h> #include <timestamp.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -86,6 +88,9 @@ void romstage(void) void platform_prog_run(struct prog *prog) { + /* We'll switch to a new stack, so validate our old one here. */ + checkstack(_estack, 0); + ccplex_cpu_start(prog_entry(prog)); clock_halt_avp(); diff --git a/src/soc/nvidia/tegra210/stage_entry.S b/src/soc/nvidia/tegra210/stage_entry.S index f5dabcb371..0eeffce2da 100644 --- a/src/soc/nvidia/tegra210/stage_entry.S +++ b/src/soc/nvidia/tegra210/stage_entry.S @@ -82,10 +82,10 @@ ENTRY(stage_entry) t210_a57_fixup - b arm64_cpu_startup -ENDPROC(stage_entry) -ENTRY(tegra210_reset_handler) - t210_a57_fixup - b arm64_cpu_startup_resume -ENDPROC(tegra210_reset_handler) + /* Initialize PSTATE, SCTLR and caches to clean state, set up stack. */ + bl arm64_init_cpu + + /* Jump to Tegra-specific C entry point. */ + bl ramstage_entry +ENDPROC(stage_entry) |