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Diffstat (limited to 'src/soc/nvidia/tegra132/soc.c')
-rw-r--r--src/soc/nvidia/tegra132/soc.c66
1 files changed, 4 insertions, 62 deletions
diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c
index b845e14322..2c03db7cb9 100644
--- a/src/soc/nvidia/tegra132/soc.c
+++ b/src/soc/nvidia/tegra132/soc.c
@@ -23,6 +23,7 @@
#include <device/device.h>
#include <arch/io.h>
#include <arch/cache.h>
+#include <arch/spintable.h>
#include <cpu/cpu.h>
#include <cbmem.h>
#include <timer.h>
@@ -61,62 +62,6 @@ static void soc_read_resources(device_t dev)
ram_resource(dev, index++, begin * KiB, size * KiB);
}
-static void *spintable_entry;
-static uint64_t * const spintable_magic = (void *)(uintptr_t)0x80000008;
-
-static void spintable_init(void)
-{
- extern void __wait_for_spin_table_request(void);
- const size_t spintable_entry_size = 4096;
-
- spintable_entry =
- cbmem_add(0x11111111, spintable_entry_size);
-
- memcpy(spintable_entry, __wait_for_spin_table_request,
- spintable_entry_size);
-
- /* Ensure the memory location is zero'd out. */
- *spintable_magic = 0;
-
- dcache_clean_invalidate_by_mva(spintable_magic,
- sizeof(*spintable_magic));
- dcache_clean_invalidate_by_mva(&spintable_entry,
- sizeof(spintable_entry));
- dcache_clean_invalidate_by_mva(spintable_entry, spintable_entry_size);
- dsb();
-}
-
-static void spintable_wait(void *monitor_address)
-{
- uint32_t sctlr_el2;
- uint32_t spsr_el3;
- uint32_t scr_el3;
-
- sctlr_el2 = raw_read_sctlr_el2();
- /* Make sure EL2 is in little endian without any caching enabled. */
- sctlr_el2 &= ~(1 << 25);
- sctlr_el2 &= ~(1 << 19);
- sctlr_el2 &= ~(1 << 12);
- sctlr_el2 &= ~0xf;
- raw_write_sctlr_el2(sctlr_el2);
- /* Ensure enter into EL2t with interrupts disabled. */
- spsr_el3 = (1 << 9) | (0xf << 6) | (1 << 3);
- raw_write_spsr_el3(spsr_el3);
- raw_write_elr_el3((uintptr_t)spintable_entry);
- /*
- * Lower exception level is 64 bit. HVC and SMC allowed. EL0 and EL1
- * in non-secure mode. No interrupts routed to EL3.
- */
- scr_el3 = raw_read_scr_el3();
- scr_el3 |= (1 << 10) | (1 << 8) | (0x3 << 4) | (1 << 0);
- scr_el3 &= ~((0x7 << 1) | (1 << 7) | (1 << 9) | (1 << 13) | (1 << 12));
- raw_write_scr_el3(scr_el3);
- isb();
- asm volatile(
- "mov x0, %0\n\t"
- "eret\n\t" : : "r" (monitor_address) : "x0" );
-}
-
static size_t cntrl_total_cpus(void)
{
return CONFIG_MAX_CPUS;
@@ -137,16 +82,13 @@ static struct cpu_control_ops cntrl_ops = {
static void soc_init(device_t dev)
{
- struct cpu_action action = {
- .run = spintable_wait,
- .arg = spintable_magic,
- };
+ struct soc_nvidia_tegra132_config *cfg;
clock_init_arm_generic_timer();
- spintable_init();
+ cfg = dev->chip_info;
+ spintable_init((void *)cfg->spintable_addr);
arch_initialize_cpus(dev, &cntrl_ops);
- arch_run_on_cpu_async(1, &action);
}
static void soc_noop(device_t dev)