diff options
Diffstat (limited to 'src/soc/nvidia/tegra132/sdram.c')
| -rw-r--r-- | src/soc/nvidia/tegra132/sdram.c | 551 |
1 files changed, 278 insertions, 273 deletions
diff --git a/src/soc/nvidia/tegra132/sdram.c b/src/soc/nvidia/tegra132/sdram.c index 14d2b50fe1..65dce9b4cd 100644 --- a/src/soc/nvidia/tegra132/sdram.c +++ b/src/soc/nvidia/tegra132/sdram.c @@ -31,7 +31,7 @@ static void sdram_patch(uintptr_t addr, uint32_t value) { if (addr) - writel(value, (uint32_t*)addr); + write32((uint32_t *)addr, value); } static void writebits(uint32_t value, uint32_t *addr, uint32_t mask) @@ -44,7 +44,7 @@ static void sdram_configure_pmc(const struct sdram_params *param, struct tegra_pmc_regs *regs) { /* VDDP Select */ - writel(param->PmcVddpSel, ®s->vddp_sel); + write32(®s->vddp_sel, param->PmcVddpSel); udelay(param->PmcVddpSelWait); /* Set DDR pad voltage */ @@ -60,7 +60,7 @@ static void sdram_configure_pmc(const struct sdram_params *param, writebits(param->PmcNoIoPower, ®s->no_iopower, (PMC_NO_IOPOWER_MEM_MASK | PMC_NO_IOPOWER_MEM_COMP_MASK)); - writel(param->PmcRegShort, ®s->reg_short); + write32(®s->reg_short, param->PmcRegShort); } static void sdram_start_clocks(const struct sdram_params *param) @@ -100,148 +100,151 @@ static void sdram_deassert_sel_dpd(const struct sdram_params *param, static void sdram_set_swizzle(const struct sdram_params *param, struct tegra_emc_regs *regs) { - writel(param->EmcSwizzleRank0ByteCfg, ®s->swizzle_rank0_byte_cfg); - writel(param->EmcSwizzleRank0Byte0, ®s->swizzle_rank0_byte0); - writel(param->EmcSwizzleRank0Byte1, ®s->swizzle_rank0_byte1); - writel(param->EmcSwizzleRank0Byte2, ®s->swizzle_rank0_byte2); - writel(param->EmcSwizzleRank0Byte3, ®s->swizzle_rank0_byte3); - writel(param->EmcSwizzleRank1ByteCfg, ®s->swizzle_rank1_byte_cfg); - writel(param->EmcSwizzleRank1Byte0, ®s->swizzle_rank1_byte0); - writel(param->EmcSwizzleRank1Byte1, ®s->swizzle_rank1_byte1); - writel(param->EmcSwizzleRank1Byte2, ®s->swizzle_rank1_byte2); - writel(param->EmcSwizzleRank1Byte3, ®s->swizzle_rank1_byte3); + write32(®s->swizzle_rank0_byte_cfg, param->EmcSwizzleRank0ByteCfg); + write32(®s->swizzle_rank0_byte0, param->EmcSwizzleRank0Byte0); + write32(®s->swizzle_rank0_byte1, param->EmcSwizzleRank0Byte1); + write32(®s->swizzle_rank0_byte2, param->EmcSwizzleRank0Byte2); + write32(®s->swizzle_rank0_byte3, param->EmcSwizzleRank0Byte3); + write32(®s->swizzle_rank1_byte_cfg, param->EmcSwizzleRank1ByteCfg); + write32(®s->swizzle_rank1_byte0, param->EmcSwizzleRank1Byte0); + write32(®s->swizzle_rank1_byte1, param->EmcSwizzleRank1Byte1); + write32(®s->swizzle_rank1_byte2, param->EmcSwizzleRank1Byte2); + write32(®s->swizzle_rank1_byte3, param->EmcSwizzleRank1Byte3); } static void sdram_set_pad_controls(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Program the pad controls */ - writel(param->EmcXm2CmdPadCtrl, ®s->xm2cmdpadctrl); - writel(param->EmcXm2CmdPadCtrl2, ®s->xm2cmdpadctrl2); - writel(param->EmcXm2CmdPadCtrl3, ®s->xm2cmdpadctrl3); - writel(param->EmcXm2CmdPadCtrl4, ®s->xm2cmdpadctrl4); - writel(param->EmcXm2CmdPadCtrl5, ®s->xm2cmdpadctrl5); + write32(®s->xm2cmdpadctrl, param->EmcXm2CmdPadCtrl); + write32(®s->xm2cmdpadctrl2, param->EmcXm2CmdPadCtrl2); + write32(®s->xm2cmdpadctrl3, param->EmcXm2CmdPadCtrl3); + write32(®s->xm2cmdpadctrl4, param->EmcXm2CmdPadCtrl4); + write32(®s->xm2cmdpadctrl5, param->EmcXm2CmdPadCtrl5); - writel(param->EmcXm2DqsPadCtrl, ®s->xm2dqspadctrl); - writel(param->EmcXm2DqsPadCtrl2, ®s->xm2dqspadctrl2); - writel(param->EmcXm2DqsPadCtrl3, ®s->xm2dqspadctrl3); - writel(param->EmcXm2DqsPadCtrl4, ®s->xm2dqspadctrl4); - writel(param->EmcXm2DqsPadCtrl5, ®s->xm2dqspadctrl5); - writel(param->EmcXm2DqsPadCtrl6, ®s->xm2dqspadctrl6); + write32(®s->xm2dqspadctrl, param->EmcXm2DqsPadCtrl); + write32(®s->xm2dqspadctrl2, param->EmcXm2DqsPadCtrl2); + write32(®s->xm2dqspadctrl3, param->EmcXm2DqsPadCtrl3); + write32(®s->xm2dqspadctrl4, param->EmcXm2DqsPadCtrl4); + write32(®s->xm2dqspadctrl5, param->EmcXm2DqsPadCtrl5); + write32(®s->xm2dqspadctrl6, param->EmcXm2DqsPadCtrl6); - writel(param->EmcXm2DqPadCtrl, ®s->xm2dqpadctrl); - writel(param->EmcXm2DqPadCtrl2, ®s->xm2dqpadctrl2); - writel(param->EmcXm2DqPadCtrl3, ®s->xm2dqpadctrl3); + write32(®s->xm2dqpadctrl, param->EmcXm2DqPadCtrl); + write32(®s->xm2dqpadctrl2, param->EmcXm2DqPadCtrl2); + write32(®s->xm2dqpadctrl3, param->EmcXm2DqPadCtrl3); - writel(param->EmcXm2ClkPadCtrl, ®s->xm2clkpadctrl); - writel(param->EmcXm2ClkPadCtrl2, ®s->xm2clkpadctrl2); + write32(®s->xm2clkpadctrl, param->EmcXm2ClkPadCtrl); + write32(®s->xm2clkpadctrl2, param->EmcXm2ClkPadCtrl2); - writel(param->EmcXm2CompPadCtrl, ®s->xm2comppadctrl); + write32(®s->xm2comppadctrl, param->EmcXm2CompPadCtrl); - writel(param->EmcXm2VttGenPadCtrl, ®s->xm2vttgenpadctrl); - writel(param->EmcXm2VttGenPadCtrl2, ®s->xm2vttgenpadctrl2); - writel(param->EmcXm2VttGenPadCtrl3, ®s->xm2vttgenpadctrl3); + write32(®s->xm2vttgenpadctrl, param->EmcXm2VttGenPadCtrl); + write32(®s->xm2vttgenpadctrl2, param->EmcXm2VttGenPadCtrl2); + write32(®s->xm2vttgenpadctrl3, param->EmcXm2VttGenPadCtrl3); - writel(param->EmcCttTermCtrl, ®s->ctt_term_ctrl); + write32(®s->ctt_term_ctrl, param->EmcCttTermCtrl); } static void sdram_trigger_emc_timing_update(struct tegra_emc_regs *regs) { - writel(EMC_TIMING_CONTROL_TIMING_UPDATE, ®s->timing_control); + write32(®s->timing_control, EMC_TIMING_CONTROL_TIMING_UPDATE); } static void sdram_init_mc(const struct sdram_params *param, struct tegra_mc_regs *regs) { /* Initialize MC VPR settings */ - writel(param->McDisplaySnapRing, ®s->display_snap_ring); - writel(param->McVideoProtectBom, ®s->video_protect_bom); - writel(param->McVideoProtectBomAdrHi, ®s->video_protect_bom_adr_hi); - writel(param->McVideoProtectSizeMb, ®s->video_protect_size_mb); - writel(param->McVideoProtectVprOverride, - ®s->video_protect_vpr_override); - writel(param->McVideoProtectVprOverride1, - ®s->video_protect_vpr_override1); - writel(param->McVideoProtectGpuOverride0, - ®s->video_protect_gpu_override_0); - writel(param->McVideoProtectGpuOverride1, - ®s->video_protect_gpu_override_1); + write32(®s->display_snap_ring, param->McDisplaySnapRing); + write32(®s->video_protect_bom, param->McVideoProtectBom); + write32(®s->video_protect_bom_adr_hi, + param->McVideoProtectBomAdrHi); + write32(®s->video_protect_size_mb, param->McVideoProtectSizeMb); + write32(®s->video_protect_vpr_override, + param->McVideoProtectVprOverride); + write32(®s->video_protect_vpr_override1, + param->McVideoProtectVprOverride1); + write32(®s->video_protect_gpu_override_0, + param->McVideoProtectGpuOverride0); + write32(®s->video_protect_gpu_override_1, + param->McVideoProtectGpuOverride1); /* Program SDRAM geometry paarameters */ - writel(param->McEmemAdrCfg, ®s->emem_adr_cfg); - writel(param->McEmemAdrCfgDev0, ®s->emem_adr_cfg_dev0); - writel(param->McEmemAdrCfgDev1, ®s->emem_adr_cfg_dev1); + write32(®s->emem_adr_cfg, param->McEmemAdrCfg); + write32(®s->emem_adr_cfg_dev0, param->McEmemAdrCfgDev0); + write32(®s->emem_adr_cfg_dev1, param->McEmemAdrCfgDev1); /* Program bank swizzling */ - writel(param->McEmemAdrCfgBankMask0, ®s->emem_bank_swizzle_cfg0); - writel(param->McEmemAdrCfgBankMask1, ®s->emem_bank_swizzle_cfg1); - writel(param->McEmemAdrCfgBankMask2, ®s->emem_bank_swizzle_cfg2); - writel(param->McEmemAdrCfgBankSwizzle3, ®s->emem_bank_swizzle_cfg3); + write32(®s->emem_bank_swizzle_cfg0, param->McEmemAdrCfgBankMask0); + write32(®s->emem_bank_swizzle_cfg1, param->McEmemAdrCfgBankMask1); + write32(®s->emem_bank_swizzle_cfg2, param->McEmemAdrCfgBankMask2); + write32(®s->emem_bank_swizzle_cfg3, + param->McEmemAdrCfgBankSwizzle3); /* Program external memory aperature (base and size) */ - writel(param->McEmemCfg, ®s->emem_cfg); + write32(®s->emem_cfg, param->McEmemCfg); /* Program SEC carveout (base and size) */ - writel(param->McSecCarveoutBom, ®s->sec_carveout_bom); - writel(param->McSecCarveoutAdrHi, ®s->sec_carveout_adr_hi); - writel(param->McSecCarveoutSizeMb, ®s->sec_carveout_size_mb); + write32(®s->sec_carveout_bom, param->McSecCarveoutBom); + write32(®s->sec_carveout_adr_hi, param->McSecCarveoutAdrHi); + write32(®s->sec_carveout_size_mb, param->McSecCarveoutSizeMb); /* Program MTS carveout (base and size) */ - writel(param->McMtsCarveoutBom, ®s->mts_carveout_bom); - writel(param->McMtsCarveoutAdrHi, ®s->mts_carveout_adr_hi); - writel(param->McMtsCarveoutSizeMb, ®s->mts_carveout_size_mb); + write32(®s->mts_carveout_bom, param->McMtsCarveoutBom); + write32(®s->mts_carveout_adr_hi, param->McMtsCarveoutAdrHi); + write32(®s->mts_carveout_size_mb, param->McMtsCarveoutSizeMb); /* Program the memory arbiter */ - writel(param->McEmemArbCfg, ®s->emem_arb_cfg); - writel(param->McEmemArbOutstandingReq, ®s->emem_arb_outstanding_req); - writel(param->McEmemArbTimingRcd, ®s->emem_arb_timing_rcd); - writel(param->McEmemArbTimingRp, ®s->emem_arb_timing_rp); - writel(param->McEmemArbTimingRc, ®s->emem_arb_timing_rc); - writel(param->McEmemArbTimingRas, ®s->emem_arb_timing_ras); - writel(param->McEmemArbTimingFaw, ®s->emem_arb_timing_faw); - writel(param->McEmemArbTimingRrd, ®s->emem_arb_timing_rrd); - writel(param->McEmemArbTimingRap2Pre, ®s->emem_arb_timing_rap2pre); - writel(param->McEmemArbTimingWap2Pre, ®s->emem_arb_timing_wap2pre); - writel(param->McEmemArbTimingR2R, ®s->emem_arb_timing_r2r); - writel(param->McEmemArbTimingW2W, ®s->emem_arb_timing_w2w); - writel(param->McEmemArbTimingR2W, ®s->emem_arb_timing_r2w); - writel(param->McEmemArbTimingW2R, ®s->emem_arb_timing_w2r); - writel(param->McEmemArbDaTurns, ®s->emem_arb_da_turns); - writel(param->McEmemArbDaCovers, ®s->emem_arb_da_covers); - writel(param->McEmemArbMisc0, ®s->emem_arb_misc0); - writel(param->McEmemArbMisc1, ®s->emem_arb_misc1); - writel(param->McEmemArbRing1Throttle, ®s->emem_arb_ring1_throttle); - writel(param->McEmemArbOverride, ®s->emem_arb_override); - writel(param->McEmemArbOverride1, ®s->emem_arb_override_1); - writel(param->McEmemArbRsv, ®s->emem_arb_rsv); + write32(®s->emem_arb_cfg, param->McEmemArbCfg); + write32(®s->emem_arb_outstanding_req, + param->McEmemArbOutstandingReq); + write32(®s->emem_arb_timing_rcd, param->McEmemArbTimingRcd); + write32(®s->emem_arb_timing_rp, param->McEmemArbTimingRp); + write32(®s->emem_arb_timing_rc, param->McEmemArbTimingRc); + write32(®s->emem_arb_timing_ras, param->McEmemArbTimingRas); + write32(®s->emem_arb_timing_faw, param->McEmemArbTimingFaw); + write32(®s->emem_arb_timing_rrd, param->McEmemArbTimingRrd); + write32(®s->emem_arb_timing_rap2pre, param->McEmemArbTimingRap2Pre); + write32(®s->emem_arb_timing_wap2pre, param->McEmemArbTimingWap2Pre); + write32(®s->emem_arb_timing_r2r, param->McEmemArbTimingR2R); + write32(®s->emem_arb_timing_w2w, param->McEmemArbTimingW2W); + write32(®s->emem_arb_timing_r2w, param->McEmemArbTimingR2W); + write32(®s->emem_arb_timing_w2r, param->McEmemArbTimingW2R); + write32(®s->emem_arb_da_turns, param->McEmemArbDaTurns); + write32(®s->emem_arb_da_covers, param->McEmemArbDaCovers); + write32(®s->emem_arb_misc0, param->McEmemArbMisc0); + write32(®s->emem_arb_misc1, param->McEmemArbMisc1); + write32(®s->emem_arb_ring1_throttle, param->McEmemArbRing1Throttle); + write32(®s->emem_arb_override, param->McEmemArbOverride); + write32(®s->emem_arb_override_1, param->McEmemArbOverride1); + write32(®s->emem_arb_rsv, param->McEmemArbRsv); /* Program extra snap levels for display client */ - writel(param->McDisExtraSnapLevels, ®s->dis_extra_snap_levels); + write32(®s->dis_extra_snap_levels, param->McDisExtraSnapLevels); /* Trigger MC timing update */ - writel(MC_TIMING_CONTROL_TIMING_UPDATE, ®s->timing_control); + write32(®s->timing_control, MC_TIMING_CONTROL_TIMING_UPDATE); /* Program second-level clock enable overrides */ - writel(param->McClkenOverride, ®s->clken_override); + write32(®s->clken_override, param->McClkenOverride); /* Program statistics gathering */ - writel(param->McStatControl, ®s->stat_control); + write32(®s->stat_control, param->McStatControl); } static void sdram_init_emc(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Program SDRAM geometry parameters */ - writel(param->EmcAdrCfg, ®s->adr_cfg); + write32(®s->adr_cfg, param->EmcAdrCfg); /* Program second-level clock enable overrides */ - writel(param->EmcClkenOverride, ®s->clken_override); + write32(®s->clken_override, param->EmcClkenOverride); /* Program EMC pad auto calibration */ - writel(param->EmcAutoCalInterval, ®s->auto_cal_interval); - writel(param->EmcAutoCalConfig2, ®s->auto_cal_config2); - writel(param->EmcAutoCalConfig3, ®s->auto_cal_config3); - writel(param->EmcAutoCalConfig, ®s->auto_cal_config); + write32(®s->auto_cal_interval, param->EmcAutoCalInterval); + write32(®s->auto_cal_config2, param->EmcAutoCalConfig2); + write32(®s->auto_cal_config3, param->EmcAutoCalConfig3); + write32(®s->auto_cal_config, param->EmcAutoCalConfig); udelay(param->EmcAutoCalWait); } @@ -249,129 +252,129 @@ static void sdram_set_emc_timing(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Program EMC timing configuration */ - writel(param->EmcCfg2, ®s->cfg_2); - writel(param->EmcCfgPipe, ®s->cfg_pipe); - writel(param->EmcDbg, ®s->dbg); - writel(param->EmcCmdQ, ®s->cmdq); - writel(param->EmcMc2EmcQ, ®s->mc2emcq); - writel(param->EmcMrsWaitCnt, ®s->mrs_wait_cnt); - writel(param->EmcMrsWaitCnt2, ®s->mrs_wait_cnt2); - writel(param->EmcFbioCfg5, ®s->fbio_cfg5); - writel(param->EmcRc, ®s->rc); - writel(param->EmcRfc, ®s->rfc); - writel(param->EmcRfcSlr, ®s->rfc_slr); - writel(param->EmcRas, ®s->ras); - writel(param->EmcRp, ®s->rp); - writel(param->EmcR2r, ®s->r2r); - writel(param->EmcW2w, ®s->w2w); - writel(param->EmcR2w, ®s->r2w); - writel(param->EmcW2r, ®s->w2r); - writel(param->EmcR2p, ®s->r2p); - writel(param->EmcW2p, ®s->w2p); - writel(param->EmcRdRcd, ®s->rd_rcd); - writel(param->EmcWrRcd, ®s->wr_rcd); - writel(param->EmcRrd, ®s->rrd); - writel(param->EmcRext, ®s->rext); - writel(param->EmcWext, ®s->wext); - writel(param->EmcWdv, ®s->wdv); - writel(param->EmcWdvMask, ®s->wdv_mask); - writel(param->EmcQUse, ®s->quse); - writel(param->EmcQuseWidth, ®s->quse_width); - writel(param->EmcIbdly, ®s->ibdly); - writel(param->EmcEInput, ®s->einput); - writel(param->EmcEInputDuration, ®s->einput_duration); - writel(param->EmcPutermExtra, ®s->puterm_extra); - writel(param->EmcPutermWidth, ®s->puterm_width); - writel(param->EmcPutermAdj, ®s->puterm_adj); - writel(param->EmcCdbCntl1, ®s->cdb_cntl_1); - writel(param->EmcCdbCntl2, ®s->cdb_cntl_2); - writel(param->EmcCdbCntl3, ®s->cdb_cntl_3); - writel(param->EmcQRst, ®s->qrst); - writel(param->EmcQSafe, ®s->qsafe); - writel(param->EmcRdv, ®s->rdv); - writel(param->EmcRdvMask, ®s->rdv_mask); - writel(param->EmcQpop, ®s->qpop); - writel(param->EmcCtt, ®s->ctt); - writel(param->EmcCttDuration, ®s->ctt_duration); - writel(param->EmcRefresh, ®s->refresh); - writel(param->EmcBurstRefreshNum, ®s->burst_refresh_num); - writel(param->EmcPreRefreshReqCnt, ®s->pre_refresh_req_cnt); - writel(param->EmcPdEx2Wr, ®s->pdex2wr); - writel(param->EmcPdEx2Rd, ®s->pdex2rd); - writel(param->EmcPChg2Pden, ®s->pchg2pden); - writel(param->EmcAct2Pden, ®s->act2pden); - writel(param->EmcAr2Pden, ®s->ar2pden); - writel(param->EmcRw2Pden, ®s->rw2pden); - writel(param->EmcTxsr, ®s->txsr); - writel(param->EmcTxsrDll, ®s->txsrdll); - writel(param->EmcTcke, ®s->tcke); - writel(param->EmcTckesr, ®s->tckesr); - writel(param->EmcTpd, ®s->tpd); - writel(param->EmcTfaw, ®s->tfaw); - writel(param->EmcTrpab, ®s->trpab); - writel(param->EmcTClkStable, ®s->tclkstable); - writel(param->EmcTClkStop, ®s->tclkstop); - writel(param->EmcTRefBw, ®s->trefbw); - writel(param->EmcOdtWrite, ®s->odt_write); - writel(param->EmcOdtRead, ®s->odt_read); - writel(param->EmcFbioCfg6, ®s->fbio_cfg6); - writel(param->EmcCfgDigDll, ®s->cfg_dig_dll); - writel(param->EmcCfgDigDllPeriod, ®s->cfg_dig_dll_period); + write32(®s->cfg_2, param->EmcCfg2); + write32(®s->cfg_pipe, param->EmcCfgPipe); + write32(®s->dbg, param->EmcDbg); + write32(®s->cmdq, param->EmcCmdQ); + write32(®s->mc2emcq, param->EmcMc2EmcQ); + write32(®s->mrs_wait_cnt, param->EmcMrsWaitCnt); + write32(®s->mrs_wait_cnt2, param->EmcMrsWaitCnt2); + write32(®s->fbio_cfg5, param->EmcFbioCfg5); + write32(®s->rc, param->EmcRc); + write32(®s->rfc, param->EmcRfc); + write32(®s->rfc_slr, param->EmcRfcSlr); + write32(®s->ras, param->EmcRas); + write32(®s->rp, param->EmcRp); + write32(®s->r2r, param->EmcR2r); + write32(®s->w2w, param->EmcW2w); + write32(®s->r2w, param->EmcR2w); + write32(®s->w2r, param->EmcW2r); + write32(®s->r2p, param->EmcR2p); + write32(®s->w2p, param->EmcW2p); + write32(®s->rd_rcd, param->EmcRdRcd); + write32(®s->wr_rcd, param->EmcWrRcd); + write32(®s->rrd, param->EmcRrd); + write32(®s->rext, param->EmcRext); + write32(®s->wext, param->EmcWext); + write32(®s->wdv, param->EmcWdv); + write32(®s->wdv_mask, param->EmcWdvMask); + write32(®s->quse, param->EmcQUse); + write32(®s->quse_width, param->EmcQuseWidth); + write32(®s->ibdly, param->EmcIbdly); + write32(®s->einput, param->EmcEInput); + write32(®s->einput_duration, param->EmcEInputDuration); + write32(®s->puterm_extra, param->EmcPutermExtra); + write32(®s->puterm_width, param->EmcPutermWidth); + write32(®s->puterm_adj, param->EmcPutermAdj); + write32(®s->cdb_cntl_1, param->EmcCdbCntl1); + write32(®s->cdb_cntl_2, param->EmcCdbCntl2); + write32(®s->cdb_cntl_3, param->EmcCdbCntl3); + write32(®s->qrst, param->EmcQRst); + write32(®s->qsafe, param->EmcQSafe); + write32(®s->rdv, param->EmcRdv); + write32(®s->rdv_mask, param->EmcRdvMask); + write32(®s->qpop, param->EmcQpop); + write32(®s->ctt, param->EmcCtt); + write32(®s->ctt_duration, param->EmcCttDuration); + write32(®s->refresh, param->EmcRefresh); + write32(®s->burst_refresh_num, param->EmcBurstRefreshNum); + write32(®s->pre_refresh_req_cnt, param->EmcPreRefreshReqCnt); + write32(®s->pdex2wr, param->EmcPdEx2Wr); + write32(®s->pdex2rd, param->EmcPdEx2Rd); + write32(®s->pchg2pden, param->EmcPChg2Pden); + write32(®s->act2pden, param->EmcAct2Pden); + write32(®s->ar2pden, param->EmcAr2Pden); + write32(®s->rw2pden, param->EmcRw2Pden); + write32(®s->txsr, param->EmcTxsr); + write32(®s->txsrdll, param->EmcTxsrDll); + write32(®s->tcke, param->EmcTcke); + write32(®s->tckesr, param->EmcTckesr); + write32(®s->tpd, param->EmcTpd); + write32(®s->tfaw, param->EmcTfaw); + write32(®s->trpab, param->EmcTrpab); + write32(®s->tclkstable, param->EmcTClkStable); + write32(®s->tclkstop, param->EmcTClkStop); + write32(®s->trefbw, param->EmcTRefBw); + write32(®s->odt_write, param->EmcOdtWrite); + write32(®s->odt_read, param->EmcOdtRead); + write32(®s->fbio_cfg6, param->EmcFbioCfg6); + write32(®s->cfg_dig_dll, param->EmcCfgDigDll); + write32(®s->cfg_dig_dll_period, param->EmcCfgDigDllPeriod); /* Don't write bit 1: addr swizzle lock bit. Written at end of sequence. */ - writel(param->EmcFbioSpare & 0xfffffffd, ®s->fbio_spare); - - writel(param->EmcCfgRsv, ®s->cfg_rsv); - writel(param->EmcDllXformDqs0, ®s->dll_xform_dqs0); - writel(param->EmcDllXformDqs1, ®s->dll_xform_dqs1); - writel(param->EmcDllXformDqs2, ®s->dll_xform_dqs2); - writel(param->EmcDllXformDqs3, ®s->dll_xform_dqs3); - writel(param->EmcDllXformDqs4, ®s->dll_xform_dqs4); - writel(param->EmcDllXformDqs5, ®s->dll_xform_dqs5); - writel(param->EmcDllXformDqs6, ®s->dll_xform_dqs6); - writel(param->EmcDllXformDqs7, ®s->dll_xform_dqs7); - writel(param->EmcDllXformDqs8, ®s->dll_xform_dqs8); - writel(param->EmcDllXformDqs9, ®s->dll_xform_dqs9); - writel(param->EmcDllXformDqs10, ®s->dll_xform_dqs10); - writel(param->EmcDllXformDqs11, ®s->dll_xform_dqs11); - writel(param->EmcDllXformDqs12, ®s->dll_xform_dqs12); - writel(param->EmcDllXformDqs13, ®s->dll_xform_dqs13); - writel(param->EmcDllXformDqs14, ®s->dll_xform_dqs14); - writel(param->EmcDllXformDqs15, ®s->dll_xform_dqs15); - writel(param->EmcDllXformQUse0, ®s->dll_xform_quse0); - writel(param->EmcDllXformQUse1, ®s->dll_xform_quse1); - writel(param->EmcDllXformQUse2, ®s->dll_xform_quse2); - writel(param->EmcDllXformQUse3, ®s->dll_xform_quse3); - writel(param->EmcDllXformQUse4, ®s->dll_xform_quse4); - writel(param->EmcDllXformQUse5, ®s->dll_xform_quse5); - writel(param->EmcDllXformQUse6, ®s->dll_xform_quse6); - writel(param->EmcDllXformQUse7, ®s->dll_xform_quse7); - writel(param->EmcDllXformQUse8, ®s->dll_xform_quse8); - writel(param->EmcDllXformQUse9, ®s->dll_xform_quse9); - writel(param->EmcDllXformQUse10, ®s->dll_xform_quse10); - writel(param->EmcDllXformQUse11, ®s->dll_xform_quse11); - writel(param->EmcDllXformQUse12, ®s->dll_xform_quse12); - writel(param->EmcDllXformQUse13, ®s->dll_xform_quse13); - writel(param->EmcDllXformQUse14, ®s->dll_xform_quse14); - writel(param->EmcDllXformQUse15, ®s->dll_xform_quse15); - writel(param->EmcDllXformDq0, ®s->dll_xform_dq0); - writel(param->EmcDllXformDq1, ®s->dll_xform_dq1); - writel(param->EmcDllXformDq2, ®s->dll_xform_dq2); - writel(param->EmcDllXformDq3, ®s->dll_xform_dq3); - writel(param->EmcDllXformDq4, ®s->dll_xform_dq4); - writel(param->EmcDllXformDq5, ®s->dll_xform_dq5); - writel(param->EmcDllXformDq6, ®s->dll_xform_dq6); - writel(param->EmcDllXformDq7, ®s->dll_xform_dq7); - writel(param->EmcDllXformAddr0, ®s->dll_xform_addr0); - writel(param->EmcDllXformAddr1, ®s->dll_xform_addr1); - writel(param->EmcDllXformAddr2, ®s->dll_xform_addr2); - writel(param->EmcDllXformAddr3, ®s->dll_xform_addr3); - writel(param->EmcDllXformAddr4, ®s->dll_xform_addr4); - writel(param->EmcDllXformAddr5, ®s->dll_xform_addr5); - writel(param->EmcAcpdControl, ®s->acpd_control); - writel(param->EmcDsrVttgenDrv, ®s->dsr_vttgen_drv); - writel(param->EmcTxdsrvttgen, ®s->txdsrvttgen); - writel(param->EmcBgbiasCtl0, ®s->bgbias_ctl0); + write32(®s->fbio_spare, param->EmcFbioSpare & 0xfffffffd); + + write32(®s->cfg_rsv, param->EmcCfgRsv); + write32(®s->dll_xform_dqs0, param->EmcDllXformDqs0); + write32(®s->dll_xform_dqs1, param->EmcDllXformDqs1); + write32(®s->dll_xform_dqs2, param->EmcDllXformDqs2); + write32(®s->dll_xform_dqs3, param->EmcDllXformDqs3); + write32(®s->dll_xform_dqs4, param->EmcDllXformDqs4); + write32(®s->dll_xform_dqs5, param->EmcDllXformDqs5); + write32(®s->dll_xform_dqs6, param->EmcDllXformDqs6); + write32(®s->dll_xform_dqs7, param->EmcDllXformDqs7); + write32(®s->dll_xform_dqs8, param->EmcDllXformDqs8); + write32(®s->dll_xform_dqs9, param->EmcDllXformDqs9); + write32(®s->dll_xform_dqs10, param->EmcDllXformDqs10); + write32(®s->dll_xform_dqs11, param->EmcDllXformDqs11); + write32(®s->dll_xform_dqs12, param->EmcDllXformDqs12); + write32(®s->dll_xform_dqs13, param->EmcDllXformDqs13); + write32(®s->dll_xform_dqs14, param->EmcDllXformDqs14); + write32(®s->dll_xform_dqs15, param->EmcDllXformDqs15); + write32(®s->dll_xform_quse0, param->EmcDllXformQUse0); + write32(®s->dll_xform_quse1, param->EmcDllXformQUse1); + write32(®s->dll_xform_quse2, param->EmcDllXformQUse2); + write32(®s->dll_xform_quse3, param->EmcDllXformQUse3); + write32(®s->dll_xform_quse4, param->EmcDllXformQUse4); + write32(®s->dll_xform_quse5, param->EmcDllXformQUse5); + write32(®s->dll_xform_quse6, param->EmcDllXformQUse6); + write32(®s->dll_xform_quse7, param->EmcDllXformQUse7); + write32(®s->dll_xform_quse8, param->EmcDllXformQUse8); + write32(®s->dll_xform_quse9, param->EmcDllXformQUse9); + write32(®s->dll_xform_quse10, param->EmcDllXformQUse10); + write32(®s->dll_xform_quse11, param->EmcDllXformQUse11); + write32(®s->dll_xform_quse12, param->EmcDllXformQUse12); + write32(®s->dll_xform_quse13, param->EmcDllXformQUse13); + write32(®s->dll_xform_quse14, param->EmcDllXformQUse14); + write32(®s->dll_xform_quse15, param->EmcDllXformQUse15); + write32(®s->dll_xform_dq0, param->EmcDllXformDq0); + write32(®s->dll_xform_dq1, param->EmcDllXformDq1); + write32(®s->dll_xform_dq2, param->EmcDllXformDq2); + write32(®s->dll_xform_dq3, param->EmcDllXformDq3); + write32(®s->dll_xform_dq4, param->EmcDllXformDq4); + write32(®s->dll_xform_dq5, param->EmcDllXformDq5); + write32(®s->dll_xform_dq6, param->EmcDllXformDq6); + write32(®s->dll_xform_dq7, param->EmcDllXformDq7); + write32(®s->dll_xform_addr0, param->EmcDllXformAddr0); + write32(®s->dll_xform_addr1, param->EmcDllXformAddr1); + write32(®s->dll_xform_addr2, param->EmcDllXformAddr2); + write32(®s->dll_xform_addr3, param->EmcDllXformAddr3); + write32(®s->dll_xform_addr4, param->EmcDllXformAddr4); + write32(®s->dll_xform_addr5, param->EmcDllXformAddr5); + write32(®s->acpd_control, param->EmcAcpdControl); + write32(®s->dsr_vttgen_drv, param->EmcDsrVttgenDrv); + write32(®s->txdsrvttgen, param->EmcTxdsrvttgen); + write32(®s->bgbias_ctl0, param->EmcBgbiasCtl0); /* * Set pipe bypass enable bits before sending any DRAM commands. @@ -391,8 +394,8 @@ static void sdram_patch_bootrom(const struct sdram_params *param, BOOT_ROM_PATCH_CONTROL_OFFSET_MASK) >> BOOT_ROM_PATCH_CONTROL_OFFSET_SHIFT); addr = BOOT_ROM_PATCH_CONTROL_BASE_ADDRESS + (addr << 2); - writel(param->BootRomPatchData, (uint32_t *)addr); - writel(1, ®s->timing_control); + write32((uint32_t *)addr, param->BootRomPatchData); + write32(®s->timing_control, 1); } } @@ -400,7 +403,7 @@ static void sdram_set_dpd3(const struct sdram_params *param, struct tegra_pmc_regs *regs) { /* Program DPD request */ - writel(param->PmcIoDpd3Req, ®s->io_dpd3_req); + write32(®s->io_dpd3_req, param->PmcIoDpd3Req); udelay(param->PmcIoDpd3ReqWait); } @@ -408,27 +411,27 @@ static void sdram_set_dli_trims(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Program DLI trims */ - writel(param->EmcDliTrimTxDqs0, ®s->dli_trim_txdqs0); - writel(param->EmcDliTrimTxDqs1, ®s->dli_trim_txdqs1); - writel(param->EmcDliTrimTxDqs2, ®s->dli_trim_txdqs2); - writel(param->EmcDliTrimTxDqs3, ®s->dli_trim_txdqs3); - writel(param->EmcDliTrimTxDqs4, ®s->dli_trim_txdqs4); - writel(param->EmcDliTrimTxDqs5, ®s->dli_trim_txdqs5); - writel(param->EmcDliTrimTxDqs6, ®s->dli_trim_txdqs6); - writel(param->EmcDliTrimTxDqs7, ®s->dli_trim_txdqs7); - writel(param->EmcDliTrimTxDqs8, ®s->dli_trim_txdqs8); - writel(param->EmcDliTrimTxDqs9, ®s->dli_trim_txdqs9); - writel(param->EmcDliTrimTxDqs10, ®s->dli_trim_txdqs10); - writel(param->EmcDliTrimTxDqs11, ®s->dli_trim_txdqs11); - writel(param->EmcDliTrimTxDqs12, ®s->dli_trim_txdqs12); - writel(param->EmcDliTrimTxDqs13, ®s->dli_trim_txdqs13); - writel(param->EmcDliTrimTxDqs14, ®s->dli_trim_txdqs14); - writel(param->EmcDliTrimTxDqs15, ®s->dli_trim_txdqs15); - - writel(param->EmcCaTrainingTimingCntl1, - ®s->ca_training_timing_cntl1); - writel(param->EmcCaTrainingTimingCntl2, - ®s->ca_training_timing_cntl2); + write32(®s->dli_trim_txdqs0, param->EmcDliTrimTxDqs0); + write32(®s->dli_trim_txdqs1, param->EmcDliTrimTxDqs1); + write32(®s->dli_trim_txdqs2, param->EmcDliTrimTxDqs2); + write32(®s->dli_trim_txdqs3, param->EmcDliTrimTxDqs3); + write32(®s->dli_trim_txdqs4, param->EmcDliTrimTxDqs4); + write32(®s->dli_trim_txdqs5, param->EmcDliTrimTxDqs5); + write32(®s->dli_trim_txdqs6, param->EmcDliTrimTxDqs6); + write32(®s->dli_trim_txdqs7, param->EmcDliTrimTxDqs7); + write32(®s->dli_trim_txdqs8, param->EmcDliTrimTxDqs8); + write32(®s->dli_trim_txdqs9, param->EmcDliTrimTxDqs9); + write32(®s->dli_trim_txdqs10, param->EmcDliTrimTxDqs10); + write32(®s->dli_trim_txdqs11, param->EmcDliTrimTxDqs11); + write32(®s->dli_trim_txdqs12, param->EmcDliTrimTxDqs12); + write32(®s->dli_trim_txdqs13, param->EmcDliTrimTxDqs13); + write32(®s->dli_trim_txdqs14, param->EmcDliTrimTxDqs14); + write32(®s->dli_trim_txdqs15, param->EmcDliTrimTxDqs15); + + write32(®s->ca_training_timing_cntl1, + param->EmcCaTrainingTimingCntl1); + write32(®s->ca_training_timing_cntl2, + param->EmcCaTrainingTimingCntl2); sdram_trigger_emc_timing_update(regs); udelay(param->EmcTimingControlWait); @@ -444,7 +447,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, * Assert dummy read of PIN register to ensure above write to PIN * register went through. 200 is the recommended value by NVIDIA. */ - dummy |= readl(®s->pin); + dummy |= read32(®s->pin); udelay(200 + param->EmcPinExtraWait); /* Deassert reset */ @@ -453,7 +456,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, * Assert dummy read of PIN register to ensure above write to PIN * register went through. 200 is the recommended value by NVIDIA. */ - dummy |= readl(®s->pin); + dummy |= read32(®s->pin); udelay(500 + param->EmcPinExtraWait); /* Enable clock enable signal */ @@ -462,7 +465,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, * Assert dummy read of PIN register to ensure above write to PIN * register went through. 200 is the recommended value by NVIDIA. */ - dummy |= readl(®s->pin); + dummy |= read32(®s->pin); udelay(param->EmcPinProgramWait); if (!dummy) { @@ -479,20 +482,20 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, static void sdram_init_ddr3(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Write mode registers */ - writel(param->EmcEmrs2, ®s->emrs2); - writel(param->EmcEmrs3, ®s->emrs3); - writel(param->EmcEmrs, ®s->emrs); - writel(param->EmcMrs, ®s->mrs); + write32(®s->emrs2, param->EmcEmrs2); + write32(®s->emrs3, param->EmcEmrs3); + write32(®s->emrs, param->EmcEmrs); + write32(®s->mrs, param->EmcMrs); if (param->EmcExtraModeRegWriteEnable) { - writel(param->EmcMrsExtra, ®s->mrs); + write32(®s->mrs, param->EmcMrsExtra); } - writel(param->EmcZcalInitDev0, ®s->zq_cal); + write32(®s->zq_cal, param->EmcZcalInitDev0); udelay(param->EmcZcalInitWait); if ((param->EmcDevSelect & 2) == 0) { - writel(param->EmcZcalInitDev1, ®s->zq_cal); + write32(®s->zq_cal, param->EmcZcalInitDev1); udelay(param->EmcZcalInitWait); } } @@ -500,29 +503,30 @@ static void sdram_init_ddr3(const struct sdram_params *param, struct tegra_emc_r static void sdram_init_lpddr3(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Precharge all banks. DEV_SELECTN = 0 => Select all devices */ - writel(((param->EmcDevSelect << EMC_REF_DEV_SELECTN_SHIFT) | 1), ®s->pre); + write32(®s->pre, + ((param->EmcDevSelect << EMC_REF_DEV_SELECTN_SHIFT) | 1)); /* Send Reset MRW command */ - writel(param->EmcMrwResetCommand, ®s->mrw); + write32(®s->mrw, param->EmcMrwResetCommand); udelay(param->EmcMrwResetNInitWait); - writel(param->EmcZcalInitDev0, ®s->mrw); + write32(®s->mrw, param->EmcZcalInitDev0); udelay(param->EmcZcalInitWait); if ((param->EmcDevSelect & 2) == 0) { - writel(param->EmcZcalInitDev1, ®s->mrw); + write32(®s->mrw, param->EmcZcalInitDev1); udelay(param->EmcZcalInitWait); } /* Write mode registers */ - writel(param->EmcMrw2, ®s->mrw2); - writel(param->EmcMrw1, ®s->mrw); - writel(param->EmcMrw3, ®s->mrw3); - writel(param->EmcMrw4, ®s->mrw4); + write32(®s->mrw2, param->EmcMrw2); + write32(®s->mrw, param->EmcMrw1); + write32(®s->mrw3, param->EmcMrw3); + write32(®s->mrw4, param->EmcMrw4); if (param->EmcExtraModeRegWriteEnable) { - writel(param->EmcMrwExtra, ®s->mrw); + write32(®s->mrw, param->EmcMrwExtra); } } @@ -546,9 +550,9 @@ static void sdram_set_zq_calibration(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Start periodic ZQ calibration */ - writel(param->EmcZcalInterval, ®s->zcal_interval); - writel(param->EmcZcalWaitCnt, ®s->zcal_wait_cnt); - writel(param->EmcZcalMrwCmd, ®s->zcal_mrw_cmd); + write32(®s->zcal_interval, param->EmcZcalInterval); + write32(®s->zcal_wait_cnt, param->EmcZcalWaitCnt); + write32(®s->zcal_mrw_cmd, param->EmcZcalMrwCmd); } static void sdram_set_refresh(const struct sdram_params *param, @@ -566,15 +570,15 @@ static void sdram_set_refresh(const struct sdram_params *param, } /* Enable refresh */ - writel((param->EmcDevSelect | EMC_REFCTRL_REF_VALID_ENABLED), - ®s->refctrl); + write32(®s->refctrl, + (param->EmcDevSelect | EMC_REFCTRL_REF_VALID_ENABLED)); - writel(param->EmcDynSelfRefControl, ®s->dyn_self_ref_control); - writel(param->EmcCfg, ®s->cfg); - writel(param->EmcSelDpdCtrl, ®s->sel_dpd_ctrl); + write32(®s->dyn_self_ref_control, param->EmcDynSelfRefControl); + write32(®s->cfg, param->EmcCfg); + write32(®s->sel_dpd_ctrl, param->EmcSelDpdCtrl); /* Write addr swizzle lock bit */ - writel(param->EmcFbioSpare, ®s->fbio_spare); + write32(®s->fbio_spare, param->EmcFbioSpare); /* Re-trigger timing to latch power saving functions */ sdram_trigger_emc_timing_update(regs); @@ -592,12 +596,13 @@ static void sdram_lock_carveouts(const struct sdram_params *param, struct tegra_mc_regs *regs) { /* Lock carveouts, and emem_cfg registers */ - writel(param->McVideoProtectWriteAccess, ®s->video_protect_reg_ctrl); - writel(MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED, - ®s->emem_cfg_access_ctrl); - writel(param->McSecCarveoutProtectWriteAccess, - ®s->sec_carveout_reg_ctrl); - writel(param->McMtsCarveoutRegCtrl, ®s->mts_carveout_reg_ctrl); + write32(®s->video_protect_reg_ctrl, + param->McVideoProtectWriteAccess); + write32(®s->emem_cfg_access_ctrl, + MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED); + write32(®s->sec_carveout_reg_ctrl, + param->McSecCarveoutProtectWriteAccess); + write32(®s->mts_carveout_reg_ctrl, param->McMtsCarveoutRegCtrl); } void sdram_init(const struct sdram_params *param) @@ -653,7 +658,7 @@ void sdram_init(const struct sdram_params *param) uint32_t sdram_get_ram_code(void) { struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs*)TEGRA_PMC_BASE; - return ((readl(&pmc->strapping_opt_a) & + return ((read32(&pmc->strapping_opt_a) & PMC_STRAPPING_OPT_A_RAM_CODE_MASK) >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT); } |