aboutsummaryrefslogtreecommitdiff
path: root/src/soc/nvidia/tegra132/cpu_lib.S
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/nvidia/tegra132/cpu_lib.S')
-rw-r--r--src/soc/nvidia/tegra132/cpu_lib.S27
1 files changed, 27 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra132/cpu_lib.S b/src/soc/nvidia/tegra132/cpu_lib.S
new file mode 100644
index 0000000000..6d458d3ab7
--- /dev/null
+++ b/src/soc/nvidia/tegra132/cpu_lib.S
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+.text
+.global smp_processor_id
+smp_processor_id:
+ /* Core 0 and 1 are encoded in the Aff0 (7:0) field of MPIDR_EL1. */
+ mrs x0, mpidr_el1
+ uxtb w0, w0
+ ret