diff options
Diffstat (limited to 'src/soc/nvidia/tegra124')
| -rw-r--r-- | src/soc/nvidia/tegra124/Kconfig | 87 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra124/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra124/bootblock_asm.S | 20 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra124/cbfs.c | 4 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra124/clock.c | 3 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra124/memlayout.ld | 48 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra124/sdram.c | 3 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra124/soc.c | 7 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra124/verstage.c | 7 |
9 files changed, 67 insertions, 114 deletions
diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index acc6e7e960..1680f4554c 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -22,34 +22,6 @@ config BOOTBLOCK_CPU_INIT bootblock must load microcode or copy data from ROM before searching for the bootblock. -# ROM image layout. -# -# 0x00000 Combined bootblock and BCT blob -# 0x18000 Master CBFS header. -# 0x18080 Free for CBFS data. -# -# iRAM (256k) layout. -# (Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself, -# so the bootblock loading address must be placed after that. After the -# handoff that area may be reclaimed for other uses, e.g. CBFS cache.) -# -# 0x4000_0000 TTB (16K+32B). 32B is for L1 table of LPAE. -# 0x4000_4020 CBFS mapping cache (96K-32B) -# 0x4001_C000 Stack (16KB... don't reduce without comparing LZMA scratchpad!). -# 0x4002_0000 Bootblock (max 48KB). -# 0x4002_C000 ROM stage (max 80KB). -# 0x4003_FFFF End of iRAM. -# -# if VBOOT2_VERIFY_FIRMWARE, -# 0x4000_0000 TTB (16K+32B). 32B is for L1 table of LPAE. -# 0x4000_4020 CBMEM console area (8K-32B) -# 0x4000_6000 CBFS mapping cache (72K) -# 0x4001_8000 vboot work buffer (16K) -# 0x4001_C000 Stack (16KB... don't reduce without comparing LZMA scratchpad!). -# 0x4002_0000 bootblock and romstage (max 70KB). -# 0x4003_1000 verstage (max 60KB). -# 0x4003_FFFF End of iRAM. - config BOOTBLOCK_ROM_OFFSET hex default 0x0 @@ -62,65 +34,6 @@ config CBFS_ROM_OFFSET hex "offset of CBFS data in ROM" default 0x18080 -config SYS_SDRAM_BASE - hex - default 0x80000000 - -config BOOTBLOCK_BASE - hex - default 0x40020000 - -# this has to be big enough to leave room big enough for the larger of the -# bootblock and the romstage. -config VERSTAGE_BASE - hex - default 0x40031000 - -# with vboot2, romstage is loaded over to the bootblock space -config ROMSTAGE_BASE - hex - default 0x40020000 if VBOOT2_VERIFY_FIRMWARE - default 0x4002c000 - -config RAMSTAGE_BASE - hex - default 0x80200000 - -config STACK_TOP - hex - default 0x40020000 - -config STACK_BOTTOM - hex - default 0x4001c000 - -# This is the ramstage thread stack, *not* the same as above! Currently unused. -config STACK_SIZE - hex - default 0x800 - -# TTB needs to be aligned to 16KB. Stick it in iRAM. -config TTB_BUFFER - hex "memory address of the TTB buffer" - default 0x40000000 - -config CBFS_CACHE_ADDRESS - hex "memory address to put CBFS cache data" - default 0x40004020 - -config CBFS_CACHE_SIZE - hex "size of CBFS cache data" - default 0x00012000 if VBOOT2_VERIFY_FIRMWARE - default 0x00016000 - -config VBOOT_WORK_BUFFER_ADDRESS - hex "memory address of vboot work buffer" - default 0x40018000 - -config VBOOT_WORK_BUFFER_SIZE - hex "size of vboot work buffer" - default 0x00004000 - config TEGRA124_MODEL_TD570D bool "TD570D" diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index d32580e96b..6de142d4ce 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -103,6 +103,6 @@ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BCT_BIN) $(CBOOTIMAGE) echo "Version = 1;" > $(BCT_WRAPPER) echo "Redundancy = 1;" >> $(BCT_WRAPPER) echo "Bctfile = $(BCT_BIN);" >> $(BCT_WRAPPER) - echo "BootLoader = $<,$(CONFIG_BOOTBLOCK_BASE),$(CONFIG_BOOTBLOCK_BASE),Complete;" >> $(BCT_WRAPPER) + echo "BootLoader = $<,$(call loadaddr,bootblock),$(call loadaddr,bootblock),Complete;" >> $(BCT_WRAPPER) @printf " CBOOTIMAGE $(subst $(obj)/,,$(@))\n" $(CBOOTIMAGE) $(BCT_WRAPPER) $@ diff --git a/src/soc/nvidia/tegra124/bootblock_asm.S b/src/soc/nvidia/tegra124/bootblock_asm.S index e4d43029fe..1a30dda65e 100644 --- a/src/soc/nvidia/tegra124/bootblock_asm.S +++ b/src/soc/nvidia/tegra124/bootblock_asm.S @@ -44,10 +44,8 @@ ENTRY(_start) * Initialize the stack to a known value. This is used to check for * stack overflow later in the boot process. */ - ldr r0, .Stack - ldr r1, .Stack_size - sub r0, r0, r1 - ldr r1, .Stack + ldr r0, =_stack + ldr r1, =_estack ldr r2, =0xdeadbeef init_stack_loop: str r2, [r0] @@ -57,7 +55,7 @@ init_stack_loop: /* Set stackpointer in internal RAM to call bootblock main() */ call_bootblock: - ldr sp, .Stack /* Set up stack pointer */ + ldr sp, =_estack /* Set up stack pointer */ ldr r0,=0x00000000 /* * The current design of cpu_info places the @@ -75,15 +73,3 @@ call_bootblock: */ bl main ENDPROC(_start) - -/* we do it this way because it's a 32-bit constant and - * in some cases too far away to be loaded as just an offset - * from IP - */ -.align 2 -.Stack: - .word CONFIG_STACK_TOP -.align 2 -/* create this size the same way we do in coreboot_ram.ld: top-bottom */ -.Stack_size: - .word CONFIG_STACK_TOP - CONFIG_STACK_BOTTOM diff --git a/src/soc/nvidia/tegra124/cbfs.c b/src/soc/nvidia/tegra124/cbfs.c index 4497d6aa27..d56050d04c 100644 --- a/src/soc/nvidia/tegra124/cbfs.c +++ b/src/soc/nvidia/tegra124/cbfs.c @@ -19,12 +19,12 @@ #include <cbfs.h> /* This driver serves as a CBFS media source. */ +#include <symbols.h> #include "spi.h" int init_default_cbfs_media(struct cbfs_media *media) { return initialize_tegra_spi_cbfs_media(media, - (void*)CONFIG_CBFS_CACHE_ADDRESS, - CONFIG_CBFS_CACHE_SIZE); + _cbfs_cache, _cbfs_cache_size); } diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index fa332835b2..f5043af3cd 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -20,6 +20,7 @@ #include <soc/addressmap.h> #include <soc/clock.h> #include <stdlib.h> +#include <symbols.h> #include <arch/clock.h> #include "clk_rst.h" #include "flow.h" @@ -485,7 +486,7 @@ void clock_cpu0_config(void *entry) { void * const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100; - write32(CONFIG_STACK_TOP, &maincpu_stack_pointer); + write32((uintptr_t)_estack, &maincpu_stack_pointer); write32((uintptr_t)entry, &maincpu_entry_point); write32((uintptr_t)&maincpu_setup, evp_cpu_reset); diff --git a/src/soc/nvidia/tegra124/memlayout.ld b/src/soc/nvidia/tegra124/memlayout.ld new file mode 100644 index 0000000000..0d9e772d41 --- /dev/null +++ b/src/soc/nvidia/tegra124/memlayout.ld @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <memlayout.h> +#include <vendorcode/google/chromeos/memlayout.h> + +#include <arch/header.ld> + +/* + * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself, + * so the bootblock loading address must be placed after that. After the + * handoff that area may be reclaimed for other uses, e.g. CBFS cache. + */ + +SECTIONS +{ + SRAM_START(0x40000000) + TTB(0x40000000, 16K + 32) + PRERAM_CBMEM_CONSOLE(0x40004020, 8K - 32) + PRERAM_CBFS_CACHE(0x40006000, 16K) + VBOOT2_WORK(0x4000A000, 16K) + STACK(0x4000E000, 8K) + BOOTBLOCK(0x40010000, 24K) + VERSTAGE(0x40016000, 72K) + ROMSTAGE(0x40028000, 96K) + SRAM_END(0x40040000) + + DRAM_START(0x80000000) + POSTRAM_CBFS_CACHE(0x80100000, 1M) + RAMSTAGE(0x80200000, 128K) + DMA_COHERENT(0x90000000, 2M) +} diff --git a/src/soc/nvidia/tegra124/sdram.c b/src/soc/nvidia/tegra124/sdram.c index f0797db652..82219b1da5 100644 --- a/src/soc/nvidia/tegra124/sdram.c +++ b/src/soc/nvidia/tegra124/sdram.c @@ -23,6 +23,7 @@ #include <soc/addressmap.h> #include <soc/clock.h> #include <stdlib.h> +#include <symbols.h> #include "emc.h" #include "mc.h" @@ -643,5 +644,5 @@ int sdram_size_mb(void) uintptr_t sdram_max_addressable_mb(void) { - return MIN((CONFIG_SYS_SDRAM_BASE/MiB) + sdram_size_mb(), 4096); + return MIN(((uintptr_t)_dram/MiB) + sdram_size_mb(), 4096); } diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c index 48e50bdc3f..5da41a9b04 100644 --- a/src/soc/nvidia/tegra124/soc.c +++ b/src/soc/nvidia/tegra124/soc.c @@ -26,6 +26,7 @@ #include <soc/nvidia/tegra124/sdram.h> #include "chip.h" #include <soc/display.h> +#include <symbols.h> #include <vendorcode/google/chromeos/chromeos.h> /* this sucks, but for now, fb size/location are hardcoded. @@ -37,12 +38,12 @@ static void soc_enable(device_t dev) u32 lcdbase = fb_base_mb(); unsigned long fb_size = FB_SIZE_MB; - ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE/KiB, + ram_resource(dev, 0, (uintptr_t)_dram/KiB, (sdram_max_addressable_mb() - fb_size)*KiB - - CONFIG_SYS_SDRAM_BASE/KiB); + (uintptr_t)_dram/KiB); mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB); - u32 sdram_end_mb = sdram_size_mb() + CONFIG_SYS_SDRAM_BASE/MiB; + u32 sdram_end_mb = sdram_size_mb() + (uintptr_t)_dram/MiB; if (sdram_end_mb > sdram_max_addressable_mb()) ram_resource(dev, 2, sdram_max_addressable_mb()*KiB, diff --git a/src/soc/nvidia/tegra124/verstage.c b/src/soc/nvidia/tegra124/verstage.c index 60361a2afd..2e5ddf276c 100644 --- a/src/soc/nvidia/tegra124/verstage.c +++ b/src/soc/nvidia/tegra124/verstage.c @@ -22,6 +22,8 @@ #include <console/console.h> #include <soc/nvidia/tegra124/cache.h> #include <soc/nvidia/tegra124/early_configs.h> +#include <stdlib.h> +#include <symbols.h> #include <vendorcode/google/chromeos/chromeos.h> static void enable_cache(void) @@ -29,8 +31,9 @@ static void enable_cache(void) mmu_init(); /* Whole space is uncached. */ mmu_config_range(0, 4096, DCACHE_OFF); - /* SRAM is cached. Round the size up to 2MB, the LPAE page size. */ - mmu_config_range(0x40000000 >> 20, 1, DCACHE_WRITEBACK); + /* SRAM is cached. MMU code will round size up to page size. */ + mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB), + DCACHE_WRITEBACK); mmu_disable_range(0, 1); dcache_mmu_enable(); } |