diff options
Diffstat (limited to 'src/soc/nvidia/tegra124/spi.c')
| -rw-r--r-- | src/soc/nvidia/tegra124/spi.c | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 27ae1faf22..007d189bc9 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -184,13 +184,13 @@ struct tegra_spi_channel *tegra_spi_init(unsigned int bus) return NULL; /* software drives chip-select, set value to high */ - setbits_le32(&spi->regs->command1, + setbits32(&spi->regs->command1, SPI_CMD1_CS_SW_HW | SPI_CMD1_CS_SW_VAL); /* 8-bit transfers, unpacked mode, most significant bit first */ - clrbits_le32(&spi->regs->command1, + clrbits32(&spi->regs->command1, SPI_CMD1_BIT_LEN_MASK | SPI_CMD1_PACKED); - setbits_le32(&spi->regs->command1, 7 << SPI_CMD1_BIT_LEN_SHIFT); + setbits32(&spi->regs->command1, 7 << SPI_CMD1_BIT_LEN_SHIFT); return spi; } @@ -265,7 +265,7 @@ static void dump_fifo_status(struct tegra_spi_channel *spi) static void clear_fifo_status(struct tegra_spi_channel *spi) { - clrbits_le32(&spi->regs->fifo_status, + clrbits32(&spi->regs->fifo_status, SPI_FIFO_STATUS_ERR | SPI_FIFO_STATUS_TX_FIFO_OVF | SPI_FIFO_STATUS_TX_FIFO_UNR | @@ -372,11 +372,11 @@ static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi, enable_mask = SPI_CMD1_RX_EN; } - setbits_le32(&spi->regs->fifo_status, flush_mask); + setbits32(&spi->regs->fifo_status, flush_mask); while (read32(&spi->regs->fifo_status) & flush_mask) ; - setbits_le32(&spi->regs->command1, enable_mask); + setbits32(&spi->regs->command1, enable_mask); /* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and * PIO transfers */ @@ -396,8 +396,8 @@ static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi, static void tegra_spi_pio_start(struct tegra_spi_channel *spi) { - setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); - setbits_le32(&spi->regs->command1, SPI_CMD1_GO); + setbits32(&spi->regs->trans_status, SPI_STATUS_RDY); + setbits32(&spi->regs->command1, SPI_CMD1_GO); /* Make sure the write to command1 completes. */ read32(&spi->regs->command1); } @@ -414,7 +414,7 @@ static int tegra_spi_pio_finish(struct tegra_spi_channel *spi) u8 *p = spi->in_buf; struct stopwatch sw; - clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN | SPI_CMD1_TX_EN); + clrbits32(&spi->regs->command1, SPI_CMD1_RX_EN | SPI_CMD1_TX_EN); /* * Allow some time in case the Rx FIFO does not yet have @@ -446,19 +446,19 @@ static void setup_dma_params(struct tegra_spi_channel *spi, struct apb_dma_channel *dma) { /* APB bus width = 8-bits, address wrap for each word */ - clrbits_le32(&dma->regs->apb_seq, + clrbits32(&dma->regs->apb_seq, APB_BUS_WIDTH_MASK << APB_BUS_WIDTH_SHIFT); /* AHB 1 word burst, bus width = 32 bits (fixed in hardware), * no address wrapping */ - clrsetbits_le32(&dma->regs->ahb_seq, + clrsetbits32(&dma->regs->ahb_seq, (AHB_BURST_MASK << AHB_BURST_SHIFT), 4 << AHB_BURST_SHIFT); /* Set ONCE mode to transfer one "block" at a time (64KB) and enable * flow control. */ - clrbits_le32(&dma->regs->csr, + clrbits32(&dma->regs->csr, APB_CSR_REQ_SEL_MASK << APB_CSR_REQ_SEL_SHIFT); - setbits_le32(&dma->regs->csr, APB_CSR_ONCE | APB_CSR_FLOW | + setbits32(&dma->regs->csr, APB_CSR_ONCE | APB_CSR_FLOW | (spi->req_sel << APB_CSR_REQ_SEL_SHIFT)); } @@ -493,7 +493,7 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi, write32(&spi->dma_out->regs->apb_ptr, (u32)&spi->regs->tx_fifo); write32(&spi->dma_out->regs->ahb_ptr, (u32)spi->out_buf); - setbits_le32(&spi->dma_out->regs->csr, APB_CSR_DIR); + setbits32(&spi->dma_out->regs->csr, APB_CSR_DIR); setup_dma_params(spi, spi->dma_out); write32(&spi->dma_out->regs->wcount, wcount); } else { @@ -506,7 +506,7 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi, write32(&spi->dma_in->regs->apb_ptr, (u32)&spi->regs->rx_fifo); write32(&spi->dma_in->regs->ahb_ptr, (u32)spi->in_buf); - clrbits_le32(&spi->dma_in->regs->csr, APB_CSR_DIR); + clrbits32(&spi->dma_in->regs->csr, APB_CSR_DIR); setup_dma_params(spi, spi->dma_in); write32(&spi->dma_in->regs->wcount, wcount); } @@ -523,12 +523,12 @@ static void tegra_spi_dma_start(struct tegra_spi_channel *spi) * (set bit to clear) between each transaction. Otherwise the next * transaction does not start. */ - setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); + setbits32(&spi->regs->trans_status, SPI_STATUS_RDY); if (spi->dma_out) - setbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); + setbits32(&spi->regs->command1, SPI_CMD1_TX_EN); if (spi->dma_in) - setbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); + setbits32(&spi->regs->command1, SPI_CMD1_RX_EN); /* * To avoid underrun conditions, enable APB DMA before SPI DMA for @@ -536,7 +536,7 @@ static void tegra_spi_dma_start(struct tegra_spi_channel *spi) */ if (spi->dma_out) dma_start(spi->dma_out); - setbits_le32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA); + setbits32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA); if (spi->dma_in) dma_start(spi->dma_in); @@ -555,7 +555,7 @@ static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) dma_busy(spi->dma_in)) ; /* this shouldn't take long, no udelay */ dma_stop(spi->dma_in); - clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); + clrbits32(&spi->regs->command1, SPI_CMD1_RX_EN); dma_release(spi->dma_in); } @@ -566,7 +566,7 @@ static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) dma_busy(spi->dma_out)) { spi_delay(spi, todo - spi_byte_count(spi)); } - clrbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); + clrbits32(&spi->regs->command1, SPI_CMD1_TX_EN); dma_stop(spi->dma_out); dma_release(spi->dma_out); } |