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path: root/src/soc/nvidia/tegra124/dma.c
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Diffstat (limited to 'src/soc/nvidia/tegra124/dma.c')
-rw-r--r--src/soc/nvidia/tegra124/dma.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/nvidia/tegra124/dma.c b/src/soc/nvidia/tegra124/dma.c
index 761bb6bce5..78a8d10e00 100644
--- a/src/soc/nvidia/tegra124/dma.c
+++ b/src/soc/nvidia/tegra124/dma.c
@@ -82,7 +82,7 @@ struct apb_dma_channel * const dma_claim(void)
* Set global enable bit, otherwise register access to channel
* DMA registers will not be possible.
*/
- setbits_le32(&apb_dma->command, APB_COMMAND_GEN);
+ setbits32(&apb_dma->command, APB_COMMAND_GEN);
for (i = 0; i < ARRAY_SIZE(apb_dma_channels); i++) {
regs = apb_dma_channels[i].regs;
@@ -122,7 +122,7 @@ void dma_release(struct apb_dma_channel * const channel)
return;
}
- clrbits_le32(&apb_dma->command, APB_COMMAND_GEN);
+ clrbits32(&apb_dma->command, APB_COMMAND_GEN);
}
int dma_start(struct apb_dma_channel * const channel)
@@ -130,7 +130,7 @@ int dma_start(struct apb_dma_channel * const channel)
struct apb_dma_channel_regs *regs = channel->regs;
/* Set ENB bit for this channel */
- setbits_le32(&regs->csr, APB_CSR_ENB);
+ setbits32(&regs->csr, APB_CSR_ENB);
return 0;
}
@@ -140,7 +140,7 @@ int dma_stop(struct apb_dma_channel * const channel)
struct apb_dma_channel_regs *regs = channel->regs;
/* Clear ENB bit for this channel */
- clrbits_le32(&regs->csr, APB_CSR_ENB);
+ clrbits32(&regs->csr, APB_CSR_ENB);
return 0;
}