diff options
Diffstat (limited to 'src/soc/nvidia/tegra124/display.c')
| -rw-r--r-- | src/soc/nvidia/tegra124/display.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 33769bac6d..87472efd09 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -124,12 +124,12 @@ static int update_display_mode(struct display_controller *disp_ctrl, * Currently most panels work inside clock range 50MHz~100MHz, and PLLD * has some requirements to have VCO in range 500MHz~1000MHz (see * clock.c for more detail). To simplify calculation, we set - * PixelClockDiv to 1 and ShiftClockDiv to 5. In future these values + * PixelClockDiv to 1 and ShiftClockDiv to 1. In future these values * may be calculated by clock_display, to allow wider frequency range. * * Note ShiftClockDiv is a 7.1 format value. */ - const u32 shift_clock_div = 5; + const u32 shift_clock_div = 1; WRITEL((PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT) | ((shift_clock_div - 1) * 2) << SHIFT_CLK_DIVIDER_SHIFT, &disp_ctrl->disp.disp_clk_ctrl); |