summaryrefslogtreecommitdiff
path: root/src/soc/mediatek
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/mediatek')
-rw-r--r--src/soc/mediatek/mt8186/Kconfig18
-rw-r--r--src/soc/mediatek/mt8186/Makefile.inc31
-rw-r--r--src/soc/mediatek/mt8186/bootblock.c9
-rw-r--r--src/soc/mediatek/mt8186/emi.c13
-rw-r--r--src/soc/mediatek/mt8186/include/soc/addressmap.h76
-rw-r--r--src/soc/mediatek/mt8186/include/soc/emi.h15
-rw-r--r--src/soc/mediatek/mt8186/include/soc/memlayout.ld56
-rw-r--r--src/soc/mediatek/mt8186/include/soc/pll.h23
-rw-r--r--src/soc/mediatek/mt8186/include/soc/spi.h13
-rw-r--r--src/soc/mediatek/mt8186/include/soc/timer.h13
-rw-r--r--src/soc/mediatek/mt8186/soc.c29
-rw-r--r--src/soc/mediatek/mt8186/spi.c22
12 files changed, 318 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8186/Kconfig b/src/soc/mediatek/mt8186/Kconfig
new file mode 100644
index 0000000000..28589e3bf7
--- /dev/null
+++ b/src/soc/mediatek/mt8186/Kconfig
@@ -0,0 +1,18 @@
+config SOC_MEDIATEK_MT8186
+ bool
+ default n
+ select ARCH_BOOTBLOCK_ARMV8_64
+ select ARCH_VERSTAGE_ARMV8_64
+ select ARCH_ROMSTAGE_ARMV8_64
+ select ARCH_RAMSTAGE_ARMV8_64
+ select HAVE_UART_SPECIAL
+
+if SOC_MEDIATEK_MT8186
+
+config VBOOT
+ select VBOOT_MUST_REQUEST_DISPLAY
+ select VBOOT_STARTS_IN_BOOTBLOCK
+ select VBOOT_SEPARATE_VERSTAGE
+ select VBOOT_RETURN_FROM_VERSTAGE
+
+endif
diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc
new file mode 100644
index 0000000000..c9cb305842
--- /dev/null
+++ b/src/soc/mediatek/mt8186/Makefile.inc
@@ -0,0 +1,31 @@
+ifeq ($(CONFIG_SOC_MEDIATEK_MT8186),y)
+
+bootblock-y += bootblock.c
+bootblock-y += ../common/mmu_operations.c
+bootblock-$(CONFIG_SPI_FLASH) += spi.c
+bootblock-y += ../common/timer.c
+bootblock-y += ../common/uart.c
+
+verstage-$(CONFIG_SPI_FLASH) += spi.c
+verstage-y += ../common/timer.c
+verstage-y += ../common/uart.c
+
+romstage-y += ../common/cbmem.c
+romstage-y += emi.c
+romstage-$(CONFIG_SPI_FLASH) += spi.c
+romstage-y += ../common/timer.c
+romstage-y += ../common/uart.c
+
+ramstage-y += emi.c
+ramstage-$(CONFIG_SPI_FLASH) += spi.c
+ramstage-y += soc.c
+ramstage-y += ../common/timer.c
+ramstage-y += ../common/uart.c
+
+CPPFLAGS_common += -Isrc/soc/mediatek/mt8186/include
+CPPFLAGS_common += -Isrc/soc/mediatek/common/include
+
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
+ ./util/mtkheader/gen-bl-img.py mt8183 sf $< $@
+
+endif
diff --git a/src/soc/mediatek/mt8186/bootblock.c b/src/soc/mediatek/mt8186/bootblock.c
new file mode 100644
index 0000000000..f48e78c309
--- /dev/null
+++ b/src/soc/mediatek/mt8186/bootblock.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <soc/mmu_operations.h>
+
+void bootblock_soc_init(void)
+{
+ mtk_mmu_init();
+}
diff --git a/src/soc/mediatek/mt8186/emi.c b/src/soc/mediatek/mt8186/emi.c
new file mode 100644
index 0000000000..169b3530f6
--- /dev/null
+++ b/src/soc/mediatek/mt8186/emi.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8186 Functional Specification
+ * Chapter number: 4.8
+ */
+
+#include <soc/emi.h>
+
+size_t sdram_size(void)
+{
+ return (size_t)4 * GiB;
+}
diff --git a/src/soc/mediatek/mt8186/include/soc/addressmap.h b/src/soc/mediatek/mt8186/include/soc/addressmap.h
new file mode 100644
index 0000000000..20a48addfd
--- /dev/null
+++ b/src/soc/mediatek/mt8186/include/soc/addressmap.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8186_INCLUDE_SOC_ADDRESSMAP_H__
+#define __SOC_MEDIATEK_MT8186_INCLUDE_SOC_ADDRESSMAP_H__
+
+enum {
+ MCUSYS_BASE = 0x0C530000,
+ IO_PHYS = 0x10000000,
+};
+
+enum {
+ MCUCFG_BASE = MCUSYS_BASE + 0x00008000,
+};
+
+enum {
+ CKSYS_BASE = IO_PHYS + 0x00000000,
+ INFRACFG_AO_BASE = IO_PHYS + 0x00001000,
+ IOCFG_LT_BASE = IO_PHYS + 0x00002000,
+ IOCFG_LM_BASE = IO_PHYS + 0x00002200,
+ IOCFG_LB_BASE = IO_PHYS + 0x00002400,
+ IOCFG_BL_BASE = IO_PHYS + 0x00002600,
+ IOCFG_RB_BASE = IO_PHYS + 0x00002A00,
+ IOCFG_RT_BASE = IO_PHYS + 0x00002C00,
+ GPIO_BASE = IO_PHYS + 0x00005000,
+ SPM_BASE = IO_PHYS + 0x00006000,
+ RGU_BASE = IO_PHYS + 0x00007000,
+ GPT_BASE = IO_PHYS + 0x00008000,
+ EINT_BASE = IO_PHYS + 0x0000B000,
+ APMIXED_BASE = IO_PHYS + 0x0000C000,
+ DEVAPC_AO_INFRA_PERI_BASE = IO_PHYS + 0x0000E000,
+ DEVAPC_AO_MM_BASE = IO_PHYS + 0x0000F000,
+ SYSTIMER_BASE = IO_PHYS + 0x00017000,
+ I2C0_DMA_BASE = IO_PHYS + 0x00200100,
+ I2C1_DMA_BASE = IO_PHYS + 0x00200200,
+ I2C2_DMA_BASE = IO_PHYS + 0x00200300,
+ I2C3_DMA_BASE = IO_PHYS + 0x00200480,
+ I2C4_DMA_BASE = IO_PHYS + 0x00200580,
+ I2C5_DMA_BASE = IO_PHYS + 0x00200700,
+ I2C6_DMA_BASE = IO_PHYS + 0x00200800,
+ I2C7_DMA_BASE = IO_PHYS + 0x00200900,
+ I2C8_DMA_BASE = IO_PHYS + 0x00200A80,
+ I2C9_DMA_BASE = IO_PHYS + 0x00200C00,
+ DEVAPC_BASE = IO_PHYS + 0x00207000,
+ EMI0_BASE = IO_PHYS + 0x00219000,
+ EMI0_MPU_BASE = IO_PHYS + 0x0021B000,
+ DRAMC_CHA_AO_BASE = IO_PHYS + 0x00220000,
+ SFLASH_REG_BASE = IO_PHYS + 0x01000000,
+ AUXADC_BASE = IO_PHYS + 0x01001000,
+ UART0_BASE = IO_PHYS + 0x01002000,
+ I2C7_BASE = IO_PHYS + 0x01004000,
+ I2C8_BASE = IO_PHYS + 0x01005000,
+ I2C0_BASE = IO_PHYS + 0x01007000,
+ I2C1_BASE = IO_PHYS + 0x01008000,
+ I2C2_BASE = IO_PHYS + 0x01009000,
+ SPI0_BASE = IO_PHYS + 0x0100A000,
+ I2C6_BASE = IO_PHYS + 0x0100D000,
+ I2C3_BASE = IO_PHYS + 0x0100F000,
+ SPI1_BASE = IO_PHYS + 0x01010000,
+ I2C4_BASE = IO_PHYS + 0x01011000,
+ SPI2_BASE = IO_PHYS + 0x01012000,
+ SPI3_BASE = IO_PHYS + 0x01013000,
+ SPI4_BASE = IO_PHYS + 0x01014000,
+ SPI5_BASE = IO_PHYS + 0x01015000,
+ I2C5_BASE = IO_PHYS + 0x01016000,
+ I2C9_BASE = IO_PHYS + 0x01019000,
+ SSUSB_IPPC_BASE = IO_PHYS + 0x01203E00,
+ MSDC0_BASE = IO_PHYS + 0x01230000,
+ SSUSB_SIF_BASE = IO_PHYS + 0x01CA0000,
+ EFUSEC_BASE = IO_PHYS + 0x01CB0000,
+ MIPITX_BASE = IO_PHYS + 0x01CC0000,
+ MSDC0_TOP_BASE = IO_PHYS + 0x01CD0000,
+ SMI_BASE = IO_PHYS + 0x04002000,
+ SMI_LARB0 = IO_PHYS + 0x04003000,
+ DSI0_BASE = IO_PHYS + 0x04013000,
+};
+#endif
diff --git a/src/soc/mediatek/mt8186/include/soc/emi.h b/src/soc/mediatek/mt8186/include/soc/emi.h
new file mode 100644
index 0000000000..decfa07a2e
--- /dev/null
+++ b/src/soc/mediatek/mt8186/include/soc/emi.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8186 Functional Specification
+ * Chapter number: 4.8
+ */
+
+#ifndef SOC_MEDIATEK_MT8186_EMI_H
+#define SOC_MEDIATEK_MT8186_EMI_H
+
+#include <stddef.h>
+
+size_t sdram_size(void);
+
+#endif /* SOC_MEDIATEK_MT8186_EMI_H */
diff --git a/src/soc/mediatek/mt8186/include/soc/memlayout.ld b/src/soc/mediatek/mt8186/include/soc/memlayout.ld
new file mode 100644
index 0000000000..a1700e60b5
--- /dev/null
+++ b/src/soc/mediatek/mt8186/include/soc/memlayout.ld
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <memlayout.h>
+
+#include <arch/header.ld>
+
+/*
+ * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM.
+ * It will be returned before starting the ramstage.
+ * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
+ */
+#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr)
+#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr)
+#define DRAM_INIT_CODE(addr, size) \
+ REGION(dram_init_code, addr, size, 64K)
+
+#define DRAM_DMA(addr, size) \
+ REGION(dram_dma, addr, size, 4K) \
+ _ = ASSERT(size % 4K == 0, \
+ "DRAM DMA buffer should be multiple of smallest page size (4K)!");
+
+SECTIONS
+{
+ SRAM_START(0x00100000)
+ VBOOT2_WORK(0x00100000, 12K)
+ STACK(0x00103000, 8K)
+ TTB(0x00105000, 28K)
+ DMA_COHERENT(0x0010C000, 4K)
+ TPM_TCPA_LOG(0x0010D000, 2K)
+ FMAP_CACHE(0x0010D800, 2K)
+ WATCHDOG_TOMBSTONE(0x0010E000, 4)
+ CBFS_MCACHE(0x0010E004, 7K - 4)
+ TIMESTAMP(0x0010FC00, 1K)
+ /* MT8186 has 64KB SRAM. */
+ SRAM_END(0x00110000)
+
+ SRAM_L2C_START(0x00200000)
+ /* 4K reserved for BOOTROM until BOOTBLOCK is started */
+ BOOTBLOCK(0x00201000, 60K)
+ /*
+ * The needed size can be obtained by:
+ * aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz
+ */
+ DRAM_INIT_CODE(0x00210000, 240K)
+ OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x0024c000, 272K)
+ PRERAM_CBFS_CACHE(0x00290000, 48K)
+ PRERAM_CBMEM_CONSOLE(0x0029C000, 400K)
+ SRAM_L2C_END(0x00300000)
+
+ DRAM_START(0x40000000)
+ DRAM_DMA(0x40000000, 1M)
+ POSTRAM_CBFS_CACHE(0x40100000, 2M)
+ RAMSTAGE(0x40300000, 256K)
+
+ BL31(0x54600000, 0x60000)
+}
diff --git a/src/soc/mediatek/mt8186/include/soc/pll.h b/src/soc/mediatek/mt8186/include/soc/pll.h
new file mode 100644
index 0000000000..0634a3b72e
--- /dev/null
+++ b/src/soc/mediatek/mt8186/include/soc/pll.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8186 Functional Specification
+ * Chapter number: 3.2
+ */
+
+#ifndef SOC_MEDIATEK_MT8186_PLL_H
+#define SOC_MEDIATEK_MT8186_PLL_H
+
+#include <soc/pll_common.h>
+
+/* top_div rate */
+enum {
+ CLK26M_HZ = 26 * MHz,
+};
+
+/* top_mux rate */
+enum {
+ UART_HZ = CLK26M_HZ,
+};
+
+#endif /* SOC_MEDIATEK_MT8186_PLL_H */
diff --git a/src/soc/mediatek/mt8186/include/soc/spi.h b/src/soc/mediatek/mt8186/include/soc/spi.h
new file mode 100644
index 0000000000..cf64660837
--- /dev/null
+++ b/src/soc/mediatek/mt8186/include/soc/spi.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8186 Functional Specification
+ * Chapter number: 5.6
+ */
+
+#ifndef MTK_MT8186_SPI_H
+#define MTK_MT8186_SPI_H
+
+#include <spi-generic.h>
+
+#endif
diff --git a/src/soc/mediatek/mt8186/include/soc/timer.h b/src/soc/mediatek/mt8186/include/soc/timer.h
new file mode 100644
index 0000000000..24d85295ce
--- /dev/null
+++ b/src/soc/mediatek/mt8186/include/soc/timer.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8186 Functional Specification
+ * Chapter number: 5.13
+ */
+
+#ifndef SOC_MEDIATEK_MT8186_TIMER_H
+#define SOC_MEDIATEK_MT8186_TIMER_H
+
+#include <soc/timer_v2.h>
+
+#endif
diff --git a/src/soc/mediatek/mt8186/soc.c b/src/soc/mediatek/mt8186/soc.c
new file mode 100644
index 0000000000..360893ceee
--- /dev/null
+++ b/src/soc/mediatek/mt8186/soc.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <soc/emi.h>
+#include <symbols.h>
+
+static void soc_read_resources(struct device *dev)
+{
+ ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB);
+}
+
+static void soc_init(struct device *dev)
+{
+}
+
+static struct device_operations soc_ops = {
+ .read_resources = soc_read_resources,
+ .init = soc_init,
+};
+
+static void enable_soc_dev(struct device *dev)
+{
+ dev->ops = &soc_ops;
+}
+
+struct chip_operations soc_mediatek_mt8186_ops = {
+ CHIP_NAME("SOC Mediatek MT8186")
+ .enable_dev = enable_soc_dev,
+};
diff --git a/src/soc/mediatek/mt8186/spi.c b/src/soc/mediatek/mt8186/spi.c
new file mode 100644
index 0000000000..95049250de
--- /dev/null
+++ b/src/soc/mediatek/mt8186/spi.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8186 Functional Specification
+ * Chapter number: 5.6, 5.8
+ */
+
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/spi.h>
+
+static const struct spi_ctrlr spi_flash_ctrlr = {
+ .max_xfer_size = 65535,
+};
+
+const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
+ {
+ .ctrlr = &spi_flash_ctrlr,
+ },
+};
+
+const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 21:07:04 +0000