9 files changed, 0 insertions, 10 deletions

diff --git a/src/soc/mediatek/common/include/soc/ddp_common.h b/src/soc/mediatek/common/include/soc/ddp_common.h
index e86675baa7..43893f7f88 100644
--- a/src/soc/mediatek/common/include/soc/ddp_common.h
+++ b/src/soc/mediatek/common/include/soc/ddp_common.h
@@ -6,7 +6,6 @@
 #include <soc/addressmap.h>
 #include <types.h>
 
-
 struct disp_ovl_regs {
 	u32 sta;
 	u32 inten;
@@ -113,7 +112,6 @@ check_member(disp_color_regs, width, 0xC50);
 check_member(disp_color_regs, height, 0xC54);
 static struct disp_color_regs *const disp_color0 = (void *)DISP_COLOR0_BASE;
 
-
 enum {
 	COLOR_BYPASS_ALL = BIT(7),
 	COLOR_SEQ_SEL    = BIT(13),
diff --git a/src/soc/mediatek/common/mtcmos.c b/src/soc/mediatek/common/mtcmos.c
index 71deb71c77..cbec250176 100644
--- a/src/soc/mediatek/common/mtcmos.c
+++ b/src/soc/mediatek/common/mtcmos.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-
 #include <device/mmio.h>
 #include <soc/mtcmos.h>
 #include <soc/spm.h>
diff --git a/src/soc/mediatek/mt8173/da9212.c b/src/soc/mediatek/mt8173/da9212.c
index 8c98b35f7f..e44a76f592 100644
--- a/src/soc/mediatek/mt8173/da9212.c
+++ b/src/soc/mediatek/mt8173/da9212.c
@@ -56,7 +56,6 @@ void da9212_probe(uint8_t i2c_num)
 	unsigned char device_id = 0;
 	unsigned char variant_id = 0;
 
-
 	/* select to page 4, clear REVERT at first time */
 	ret |= i2c_write_field(i2c_num, DA9212_SLAVE_ADDR,
 			       DA9212_REG_PAGE_CON, DA9212_REG_PAGE4,
diff --git a/src/soc/mediatek/mt8173/mt6311.c b/src/soc/mediatek/mt8173/mt6311.c
index e8fe6dc6d3..3e61f8c399 100644
--- a/src/soc/mediatek/mt8173/mt6311.c
+++ b/src/soc/mediatek/mt8173/mt6311.c
@@ -25,7 +25,6 @@ static void mt6311_hw_init(uint8_t i2c_num)
 	int ret = 0;
 	unsigned char var[3] = {0};
 
-
 	/*
 	 * Phase Shedding Trim Software Setting
 	 * The phase 2 of MT6311 will enter PWM mode if the threshold is
diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c
index 8a86f0b3ae..0fe94cf0c3 100644
--- a/src/soc/mediatek/mt8173/pll.c
+++ b/src/soc/mediatek/mt8173/pll.c
@@ -373,7 +373,6 @@ void mt_pll_enable_ssusb_clk(void)
 	setbits32(&mtk_apmixed->ap_pll_con2, (0x1 << 2) | (0x1 << 1));
 }
 
-
 /* after pmic_init */
 void mt_pll_post_init(void)
 {
diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c
index ef57fa6204..d08de45325 100644
--- a/src/soc/mediatek/mt8173/rtc.c
+++ b/src/soc/mediatek/mt8173/rtc.c
@@ -9,7 +9,6 @@
 
 #define RTC_GPIO_USER_MASK	  ((1 << 13) - (1 << 8))
 
-
 /* initialize rtc related gpio */
 static int rtc_gpio_init(void)
 {
diff --git a/src/soc/mediatek/mt8183/include/soc/ddp.h b/src/soc/mediatek/mt8183/include/soc/ddp.h
index bc4e6ab501..a059abf566 100644
--- a/src/soc/mediatek/mt8183/include/soc/ddp.h
+++ b/src/soc/mediatek/mt8183/include/soc/ddp.h
@@ -42,7 +42,6 @@ check_member(mmsys_cfg_regs, dpi0_sel_sout_sel_in, 0xF64);
 static struct mmsys_cfg_regs *const mmsys_cfg =
 	(void *)MMSYS_BASE;
 
-
 /* DISP_REG_CONFIG_MMSYS_CG_CON0
    Configures free-run clock gating 0
 	0: Enable clock
diff --git a/src/soc/mediatek/mt8183/pmic_wrap.c b/src/soc/mediatek/mt8183/pmic_wrap.c
index bae3fce5bf..4d195b79f0 100644
--- a/src/soc/mediatek/mt8183/pmic_wrap.c
+++ b/src/soc/mediatek/mt8183/pmic_wrap.c
@@ -47,7 +47,6 @@ enum {
 	COUNTER16_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x340),
 };
 
-
 static void pwrap_soft_reset(void)
 {
 	write32(&mt8183_infracfg->infra_globalcon_rst2_set, 0x1);
diff --git a/src/soc/mediatek/mt8192/include/soc/gpio.h b/src/soc/mediatek/mt8192/include/soc/gpio.h
index 0c90bdf8d9..716a63d08e 100644
--- a/src/soc/mediatek/mt8192/include/soc/gpio.h
+++ b/src/soc/mediatek/mt8192/include/soc/gpio.h
@@ -699,7 +699,6 @@ enum {
 		I2S6_DI, I2S8_DI, RES6, RES7),
 };
 
-
 struct val_regs {
 	uint32_t val;
 	uint32_t set;