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-rw-r--r--src/soc/mediatek/mt8188/Makefile.inc2
-rw-r--r--src/soc/mediatek/mt8188/dp_intf.c13
-rw-r--r--src/soc/mediatek/mt8188/include/soc/addressmap.h2
3 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8188/Makefile.inc b/src/soc/mediatek/mt8188/Makefile.inc
index 63c7f4aec0..ded5dfcab4 100644
--- a/src/soc/mediatek/mt8188/Makefile.inc
+++ b/src/soc/mediatek/mt8188/Makefile.inc
@@ -33,6 +33,7 @@ ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c
ramstage-y += ../common/ddp.c ddp.c
ramstage-y += ../common/devapc.c devapc.c
ramstage-y += ../common/dfd.c
+ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c dp_intf.c
ramstage-y += ../common/dpm.c
ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c
ramstage-y += ../common/emi.c
@@ -51,6 +52,7 @@ ramstage-y += ../common/usb.c usb.c
BL31_MAKEARGS += PLAT=mt8188
CPPFLAGS_common += -Isrc/soc/mediatek/mt8188/include
+CPPFLAGS_common += -Isrc/soc/mediatek/common/dp/include
CPPFLAGS_common += -Isrc/soc/mediatek/common/include
MT8188_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8188
diff --git a/src/soc/mediatek/mt8188/dp_intf.c b/src/soc/mediatek/mt8188/dp_intf.c
new file mode 100644
index 0000000000..911cf6fb65
--- /dev/null
+++ b/src/soc/mediatek/mt8188/dp_intf.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <soc/addressmap.h>
+#include <soc/dp_intf.h>
+
+const struct mtk_dpintf dpintf_data = {
+ .regs = (void *)(DP_INTF0_BASE),
+ .color_format = MTK_DPINTF_COLOR_FORMAT_RGB,
+ .yc_map = MTK_DPINTF_OUT_YC_MAP_RGB,
+ .bit_num = MTK_DPINTF_OUT_BIT_NUM_8BITS,
+ .channel_swap = MTK_DPINTF_OUT_CHANNEL_SWAP_RGB,
+ .input_mode = MTK_DPINTF_INPUT_MODE_1P,
+};
diff --git a/src/soc/mediatek/mt8188/include/soc/addressmap.h b/src/soc/mediatek/mt8188/include/soc/addressmap.h
index 904e77eee1..da95952231 100644
--- a/src/soc/mediatek/mt8188/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8188/include/soc/addressmap.h
@@ -96,9 +96,11 @@ enum {
DISP_GAMMA0_BASE = IO_PHYS + 0x0C006000,
DISP_DITHER0_BASE = IO_PHYS + 0x0C007000,
DISP_OVL1_BASE = IO_PHYS + 0x0C00A000,
+ DP_INTF0_BASE = IO_PHYS + 0x0C015000,
DISP_MUTEX_BASE = IO_PHYS + 0x0C016000,
DISP_POSTMASK0_BASE = IO_PHYS + 0x0C01A000,
VDOSYS0_BASE = IO_PHYS + 0x0C01D000,
SMI_LARB0 = IO_PHYS + 0x0C022000,
+ EDP_BASE = IO_PHYS + 0x0C500000,
};
#endif