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-rw-r--r--src/soc/mediatek/mt8195/Makefile.inc1
-rw-r--r--src/soc/mediatek/mt8195/apusys.c31
-rw-r--r--src/soc/mediatek/mt8195/include/soc/addressmap.h1
-rw-r--r--src/soc/mediatek/mt8195/include/soc/apusys.h31
-rw-r--r--src/soc/mediatek/mt8195/soc.c2
5 files changed, 66 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc
index 5d444c7564..f99fa33e0b 100644
--- a/src/soc/mediatek/mt8195/Makefile.inc
+++ b/src/soc/mediatek/mt8195/Makefile.inc
@@ -22,6 +22,7 @@ verstage-y += ../common/timer.c timer.c
verstage-y += ../common/uart.c
verstage-y += ../common/wdt.c
+ramstage-y += apusys.c
romstage-y += ../common/auxadc.c
romstage-y += ../common/cbmem.c
romstage-y += ../common/clkbuf.c
diff --git a/src/soc/mediatek/mt8195/apusys.c b/src/soc/mediatek/mt8195/apusys.c
new file mode 100644
index 0000000000..bc3c4abeca
--- /dev/null
+++ b/src/soc/mediatek/mt8195/apusys.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <soc/apusys.h>
+
+/* MBOX Functional Configuration */
+DEFINE_BITFIELD(LOCK, 0, 0)
+DEFINE_BITFIELD(NO_MPU, 16, 16)
+
+static void dump_apusys_reg(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(mt8195_apu_mbox); i++) {
+ printk(BIOS_INFO, "APU_MBOX %p = %#x\n",
+ (void *)&mt8195_apu_mbox[i]->mbox_func_cfg,
+ read32(&mt8195_apu_mbox[i]->mbox_func_cfg));
+ }
+}
+
+void apusys_init(void)
+{
+ int i;
+
+ /* Setup MBOX MPU for non secure access */
+ for (i = 0; i < ARRAY_SIZE(mt8195_apu_mbox); i++)
+ SET32_BITFIELDS(&mt8195_apu_mbox[i]->mbox_func_cfg, NO_MPU, 1, LOCK, 1);
+
+ dump_apusys_reg();
+}
diff --git a/src/soc/mediatek/mt8195/include/soc/addressmap.h b/src/soc/mediatek/mt8195/include/soc/addressmap.h
index 88b545a97e..cbe704cbb9 100644
--- a/src/soc/mediatek/mt8195/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8195/include/soc/addressmap.h
@@ -80,6 +80,7 @@ enum {
IOCFG_RB_BASE = IO_PHYS + 0x01EB0000,
IOCFG_TL_BASE = IO_PHYS + 0x01F40000,
MSDC0_TOP_BASE = IO_PHYS + 0x01F50000,
+ APU_MBOX_BASE = IO_PHYS + 0x09000000,
DISP_OVL0_BASE = IO_PHYS + 0x0C000000,
DISP_RDMA0_BASE = IO_PHYS + 0x0C002000,
DISP_COLOR0_BASE = IO_PHYS + 0x0C003000,
diff --git a/src/soc/mediatek/mt8195/include/soc/apusys.h b/src/soc/mediatek/mt8195/include/soc/apusys.h
new file mode 100644
index 0000000000..287e0f8ee0
--- /dev/null
+++ b/src/soc/mediatek/mt8195/include/soc/apusys.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8195_APUSYS_H
+#define SOC_MEDIATEK_MT8195_APUSYS_H
+
+#include <soc/addressmap.h>
+#include <types.h>
+
+struct mt8195_apu_mbox_regs {
+ u32 mbox_in[8];
+ u32 mbox_out[8];
+ u32 mbox_reserved1[28];
+ u32 mbox_func_cfg;
+ u32 mbox0_reserved2[19];
+};
+
+check_member(mt8195_apu_mbox_regs, mbox_func_cfg, 0x0b0);
+
+static struct mt8195_apu_mbox_regs * const mt8195_apu_mbox[] = {
+ (void *)APU_MBOX_BASE,
+ (void *)(APU_MBOX_BASE + 0x100),
+ (void *)(APU_MBOX_BASE + 0x200),
+ (void *)(APU_MBOX_BASE + 0x300),
+ (void *)(APU_MBOX_BASE + 0x400),
+ (void *)(APU_MBOX_BASE + 0x500),
+ (void *)(APU_MBOX_BASE + 0x600),
+ (void *)(APU_MBOX_BASE + 0x700),
+};
+
+void apusys_init(void);
+#endif /* SOC_MEDIATEK_MT8195_APUSYS_H */
diff --git a/src/soc/mediatek/mt8195/soc.c b/src/soc/mediatek/mt8195/soc.c
index 20bd226cc9..80ca3d9d11 100644
--- a/src/soc/mediatek/mt8195/soc.c
+++ b/src/soc/mediatek/mt8195/soc.c
@@ -2,6 +2,7 @@
#include <bootmem.h>
#include <device/device.h>
+#include <soc/apusys.h>
#include <soc/devapc.h>
#include <soc/dfd.h>
#include <soc/emi.h>
@@ -28,6 +29,7 @@ static void soc_init(struct device *dev)
{
mtk_mmu_disable_l2c_sram();
dapc_init();
+ apusys_init();
mcupm_init();
sspm_init();