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-rw-r--r--src/soc/mediatek/common/include/soc/eint_event.h2
-rw-r--r--src/soc/mediatek/common/mmu_operations.c2
-rw-r--r--src/soc/mediatek/mt8173/dramc_pi_basic_api.c2
-rw-r--r--src/soc/mediatek/mt8192/pll.c2
-rw-r--r--src/soc/mediatek/mt8195/pll.c2
5 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/mediatek/common/include/soc/eint_event.h b/src/soc/mediatek/common/include/soc/eint_event.h
index 98db7b04e8..6d544b4e7a 100644
--- a/src/soc/mediatek/common/include/soc/eint_event.h
+++ b/src/soc/mediatek/common/include/soc/eint_event.h
@@ -6,7 +6,7 @@
#include <device/mmio.h>
#include <soc/addressmap.h>
-/* eint event mask cler register */
+/* eint event mask clear register */
struct eint_event_reg {
uint32_t eint_event_mask_clr[7];
};
diff --git a/src/soc/mediatek/common/mmu_operations.c b/src/soc/mediatek/common/mmu_operations.c
index 960d742d63..340f9ec989 100644
--- a/src/soc/mediatek/common/mmu_operations.c
+++ b/src/soc/mediatek/common/mmu_operations.c
@@ -50,6 +50,6 @@ void mtk_mmu_disable_l2c_sram(void)
mtk_soc_disable_l2c_sram();
- /* Reenable MMU with now enlarged L2 cache. Page tables still valid. */
+ /* Re-enable MMU with now enlarged L2 cache. Page tables still valid. */
mmu_enable();
}
diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c
index 009d03a154..23a9403acf 100644
--- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c
+++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c
@@ -777,7 +777,7 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2,
* ISI 0 | 0
* AUD 0 | 1
* XTALK 1 | 0
- * UNKNOW 1 | 1
+ * UNKNOWN 1 | 1
*/
switch (testaudpat) {
case XTALK:
diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c
index f0a9509173..e49e222c7c 100644
--- a/src/soc/mediatek/mt8192/pll.c
+++ b/src/soc/mediatek/mt8192/pll.c
@@ -524,7 +524,7 @@ u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id)
SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0,
CLK_MISC_CFG_0_METER_DIV, 0);
} else {
- die("unsupport fmeter type\n");
+ die("unsupported fmeter type\n");
}
/* enable frequency meter */
diff --git a/src/soc/mediatek/mt8195/pll.c b/src/soc/mediatek/mt8195/pll.c
index 74dd1509f3..8fd424dc49 100644
--- a/src/soc/mediatek/mt8195/pll.c
+++ b/src/soc/mediatek/mt8195/pll.c
@@ -844,7 +844,7 @@ u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id)
SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0,
CLK_MISC_CFG_0_METER_DIV, 0);
} else {
- die("unsupport fmeter type\n");
+ die("unsupported fmeter type\n");
}
/* enable frequency meter */