3 files changed, 40 insertions, 0 deletions
diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h
index d9ba2308e9..ae6ad64ded 100644
--- a/src/soc/mediatek/common/include/soc/pll_common.h
+++ b/src/soc/mediatek/common/include/soc/pll_common.h
@@ -3,6 +3,7 @@
 #ifndef SOC_MEDIATEK_PLL_COMMON_H
 #define SOC_MEDIATEK_PLL_COMMON_H
 
+#include <device/mmio.h>
 #include <soc/addressmap.h>
 #include <types.h>
 
@@ -54,6 +55,15 @@ struct pll {
 		.div_rate = _div_rate,					\
 	}
 
+/* every PLL can share the same POWER_EN/ISO_EN/EN bits, use the common BITFIELD macro */
+DEFINE_BIT(PLL_ENABLE, 0)
+
+DEFINE_BIT(PLL_POWER_ENABLE, 0)
+DEFINE_BIT(PLL_ISO_ENABLE, 1)
+DEFINE_BITFIELD(PLL_POWER_ISO_ENABLE, 1, 0)
+
+DEFINE_BITFIELD(PLL_CON1, 31, 0)
+
 void pll_set_pcw_change(const struct pll *pll);
 void mux_set_sel(const struct mux *mux, u32 sel);
 int pll_set_rate(const struct pll *pll, u32 rate);
diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c
index a2a4dea1c4..cdb598fcc5 100644
--- a/src/soc/mediatek/mt8192/dramc_pi_main.c
+++ b/src/soc/mediatek/mt8192/dramc_pi_main.c
@@ -2,6 +2,8 @@
 
 #include <soc/dramc_pi_api.h>
 #include <soc/dramc_register.h>
+#include <soc/pll.h>
+#include <soc/pll_common.h>
 #include <soc/regulator.h>
 
 static void set_vcore_voltage(const struct ddr_cali *cali)
@@ -16,6 +18,25 @@ static void dramc_calibration_all_channels(struct ddr_cali *cali)
 {
 }
 
+static void mem_pll_init(void)
+{
+	SET32_BITFIELDS(&mtk_apmixed->mpll_con3, PLL_POWER_ISO_ENABLE, 3);
+
+	udelay(30);
+	SET32_BITFIELDS(&mtk_apmixed->mpll_con3, PLL_ISO_ENABLE, 0);
+
+	udelay(1);
+	SET32_BITFIELDS(&mtk_apmixed->mpll_con1, PLL_CON1, MPLL_CON1_FREQ);
+	SET32_BITFIELDS(&mtk_apmixed->mpll_con0, PLL_ENABLE, 1);
+
+	udelay(20);
+	SET32_BITFIELDS(&mtk_apmixed->pllon_con0, MPLL_IOS_SEL, 0);
+	SET32_BITFIELDS(&mtk_apmixed->pllon_con0, MPLL_EN_SEL, 0);
+	SET32_BITFIELDS(&mtk_apmixed->pllon_con1, MPLL_PWR_SEL, 0);
+	SET32_BITFIELDS(&mtk_apmixed->pllon_con2, MPLL_BY_ISO_DLY, 0);
+	SET32_BITFIELDS(&mtk_apmixed->pllon_con3, MPLL_BY_PWR_DLY, 0);
+}
+
 void init_dram(const struct dramc_data *dparam)
 {
 	u32 bc_bak;
@@ -35,6 +56,7 @@ void init_dram(const struct dramc_data *dparam)
 	cali.emi_config = &ddr_info->emi_config;
 
 	dramc_set_broadcast(DRAMC_BROADCAST_ON);
+	mem_pll_init();
 
 	global_option_init(&cali);
 	bc_bak = dramc_get_broadcast();
diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h
index 52bf3c2f38..cd1c01250c 100644
--- a/src/soc/mediatek/mt8192/include/soc/pll.h
+++ b/src/soc/mediatek/mt8192/include/soc/pll.h
@@ -241,6 +241,8 @@ check_member(mtk_apmixed_regs, ap_pllgp1_con0, 0x0200);
 check_member(mtk_apmixed_regs, ap_pllgp2_con0, 0x0300);
 check_member(mtk_apmixed_regs, usbpll_con2, 0x03cc);
 
+#define MPLL_CON1_FREQ		0x84200000
+
 enum {
 	USBPLL_EN = 0x1 << 2,
 
@@ -306,6 +308,12 @@ DEFINE_BITFIELD(CLK_MISC_CFG_0_METER_DIV, 31, 24)
 DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4)
 DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16)
 
+DEFINE_BIT(MPLL_IOS_SEL, 2)
+DEFINE_BIT(MPLL_EN_SEL, 11)
+DEFINE_BIT(MPLL_PWR_SEL, 20)
+DEFINE_BIT(MPLL_BY_ISO_DLY, 2)
+DEFINE_BIT(MPLL_BY_PWR_DLY, 2)
+
 DEFINE_BITFIELD(WDT_SWSYSRST_KEY, 31, 24)
 DEFINE_BITFIELD(WDT_SWSYSRST_CONN_MCU, 12, 12)