3 files changed, 165 insertions, 15 deletions
diff --git a/src/soc/mediatek/mt8196/include/soc/dramc_param.h b/src/soc/mediatek/mt8196/include/soc/dramc_param.h
new file mode 100644
index 0000000000..b35d518720
--- /dev/null
+++ b/src/soc/mediatek/mt8196/include/soc/dramc_param.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_MT8196_DRAMC_PARAM_H__
+#define __SOC_MEDIATEK_MT8196_DRAMC_PARAM_H__
+
+/*
+ * NOTE: This file is shared between coreboot and dram blob. Any change in this
+ * file should be synced to the other repository.
+ */
+
+#include <soc/dramc_param_common.h>
+#include <soc/dramc_soc.h>
+#include <stdint.h>
+#include <sys/types.h>
+
+#define DRAMC_PARAM_HEADER_VERSION 2
+
+struct sdram_params {
+	/* rank, cbt */
+	u32 rank_num;
+	u32 dram_cbt_mode;
+
+	u16 delay_cell_timex100;
+	u8 u18ph_dly;
+
+	/* duty */
+	s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX];
+	s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP5];
+	s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP5];
+	s8 duty_mck16x_delay[CHANNEL_MAX][DQS_NUMBER_LP5 + 1];
+	s8 duty_dq_delay[CHANNEL_MAX][DQS_NUMBER_LP5];
+	s8 duty_dqm_delay[CHANNEL_MAX][DQS_NUMBER_LP5];
+
+	/* cbt */
+	u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX];
+	u8 cbt_final_range[CHANNEL_MAX][RANK_MAX];
+	s16 cbt_cmd_dly[CHANNEL_MAX];
+	u16 cbt_cs_dly[CHANNEL_MAX];
+	u8 cbt_ca_prebit_dly[CHANNEL_MAX][DQS_BIT_NUMBER];
+
+	/* write leveling */
+	u8 wr_level_pi[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+	u8 wr_level_dly[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+
+	/* gating */
+	u8 gating_UI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+	u8 gating_PI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+	u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+	u16 wck2dqo_cnt[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+
+	/* rx input buffer */
+	s8 dq_offc[CHANNEL_MAX][DQ_DATA_WIDTH_LP5];
+	s8 dqm_offc[CHANNEL_MAX][DQS_NUMBER_LP5];
+
+	/* tx perbit */
+	u16 tx_window_vref[CHANNEL_MAX][RANK_MAX];
+	u16 tx_window_vref_range[CHANNEL_MAX][RANK_MAX];
+	u16 tx_dq[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+	u16 tx_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+	u16 tx_dqm_only[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+	u8 tx_perbit_dlyline[CHANNEL_MAX][RANK_MAX][EXT_DQ_DATA_WIDTH];
+	u16 wck2dqi_cnt0[CHANNEL_MAX][RANK_MAX];
+	u16 wck2dqi_cnt1[CHANNEL_MAX][RANK_MAX];
+
+	/* rx datlat */
+	u8 rx_datlat[CHANNEL_MAX];
+
+	/* rx perbit */
+	u8 rx_best_vref_perbyte[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+	u8 rx_best_vref_perbit[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5];
+	u16 rx_perbit_dqs[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+	u16 rx_perbit_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+	u16 rx_perbit_dq[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5];
+	s16 rx_perbit_begin;
+
+	/* dvs */
+	u8 dvs_delay[CHANNEL_MAX][DQS_NUMBER_LP5];
+	u8 perbit_dcc[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5];
+
+	/* dcm */
+	u8 best_u[CHANNEL_MAX][RANK_MAX];
+	u8 best_l[CHANNEL_MAX][RANK_MAX];
+
+	/* Read DCA */
+	s8 rdca_u[CHANNEL_MAX][RANK_MAX];
+	s8 rdca_l[CHANNEL_MAX][RANK_MAX];
+
+	/* RDCC */
+	s8 rdcc[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+
+	/* tx oe */
+	u8 tx_oe_dq_mck[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+	u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5];
+	u16 tx_oe_offset[CHANNEL_MAX][RANK_MAX];
+};
+
+struct dramc_data {
+	struct ddr_base_info ddr_info;
+	struct sdram_params freq_params[DRAM_DFS_SHU_MAX];
+};
+
+struct dramc_param {
+	struct dramc_param_header header;
+	void (*do_putc)(unsigned char c);
+	struct dramc_data dramc_datas;
+};
+
+struct dramc_param *get_dramc_param_from_blob(void *blob);
+void dump_param_header(const void *blob);
+int validate_dramc_param(const void *blob);
+int is_valid_dramc_param(const void *blob);
+int initialize_dramc_param(void *blob);
+
+#endif  /* __SOC_MEDIATEK_MT8196_DRAMC_PARAM_H__ */
diff --git a/src/soc/mediatek/mt8196/include/soc/dramc_soc.h b/src/soc/mediatek/mt8196/include/soc/dramc_soc.h
new file mode 100644
index 0000000000..dde00c23da
--- /dev/null
+++ b/src/soc/mediatek/mt8196/include/soc/dramc_soc.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8196_DRAMC_SOC_H__
+#define __SOC_MEDIATEK_MT8196_DRAMC_SOC_H__
+
+#include <soc/dramc_soc_common.h>
+#include <stdint.h>
+
+typedef enum {
+	CHANNEL_A = 0,
+	CHANNEL_B,
+	CHANNEL_C,
+	CHANNEL_D,
+	CHANNEL_MAX,
+} DRAM_CHANNEL_T;
+
+typedef enum {
+	RANK_0 = 0,
+	RANK_1,
+	RANK_MAX,
+} DRAM_RANK_T;
+
+typedef enum {
+	SRAM_SHU0 = 0,
+	SRAM_SHU1,
+	SRAM_SHU2,
+	SRAM_SHU3,
+	SRAM_SHU4,
+	SRAM_SHU5,
+	SRAM_SHU6,
+	SRAM_SHU7,
+	SRAM_SHU8,
+	SRAM_SHU9,
+	SRAM_SHU10,
+	SRAM_SHU11,
+	DRAM_DFS_SRAM_MAX
+} DRAM_DFS_SRAM_SHU_T; /* DRAM SRAM RG type */
+
+typedef enum {
+	DRVP = 0,
+	DRVN,
+	ODTN,
+	IMP_DRV_MAX,
+} DRAM_IMP_DRV_T;
+
+#define DRAM_DFS_SHU_MAX	DRAM_DFS_SRAM_MAX
+#define DQS_NUMBER_LP5		2
+#define DQ_DATA_WIDTH_LP5	16
+#define EXT_DQ_DATA_WIDTH	18
+
+#endif	/* __SOC_MEDIATEK_MT8196_DRAMC_SOC_H__ */
diff --git a/src/soc/mediatek/mt8196/include/soc/emi.h b/src/soc/mediatek/mt8196/include/soc/emi.h
deleted file mode 100644
index 6acc0cfb46..0000000000
--- a/src/soc/mediatek/mt8196/include/soc/emi.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * This file is created based on MT8196 Functional Specification
- * Chapter number: 10.2
- */
-
-#ifndef SOC_MEDIATEK_MT8196_EMI_H
-#define SOC_MEDIATEK_MT8196_EMI_H
-
-#include <stddef.h>
-
-size_t sdram_size(void);
-
-#endif /* SOC_MEDIATEK_MT8196_EMI_H */