aboutsummaryrefslogtreecommitdiff
path: root/src/soc/mediatek/mt8195/pll.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/mediatek/mt8195/pll.c')
-rw-r--r--src/soc/mediatek/mt8195/pll.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/mediatek/mt8195/pll.c b/src/soc/mediatek/mt8195/pll.c
index 06b2156702..792af7f360 100644
--- a/src/soc/mediatek/mt8195/pll.c
+++ b/src/soc/mediatek/mt8195/pll.c
@@ -755,7 +755,7 @@ void mt_pll_init(void)
* TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
*/
for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
- mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
+ pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
/* switch sram control to bypass mode for PCIE_MAC_P0 */
setbits32(&mtk_spm->ap_mdsrc_req, 0x1);
@@ -827,9 +827,9 @@ void mt_pll_set_tvd_pll1_freq(u32 freq)
udelay(PLL_EN_DELAY);
}
-void edp_mux_set_sel(u32 sel)
+void mt_pll_edp_mux_set_sel(u32 sel)
{
- mux_set_sel(&muxes[TOP_EDP_SEL], sel);
+ pll_mux_set_sel(&muxes[TOP_EDP_SEL], sel);
}
u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id)