2 files changed, 26 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h
index 442aa30877..43c2528994 100644
--- a/src/soc/mediatek/mt8192/include/soc/pll.h
+++ b/src/soc/mediatek/mt8192/include/soc/pll.h
@@ -249,6 +249,7 @@ enum {
 
 	MCU_MUX_MASK = 0x3 << 9,
 	MCU_MUX_SRC_PLL = 0x1 << 9,
+	MCU_MUX_SRC_DIV_PLL1 = 0x2 << 9,
 };
 
 enum {
diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c
index 40d92fdc63..e8849df0b0 100644
--- a/src/soc/mediatek/mt8192/pll.c
+++ b/src/soc/mediatek/mt8192/pll.c
@@ -434,3 +434,28 @@ void mt_pll_init(void)
 	/* enable [14] dramc_pll104m_ck */
 	setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14);
 }
+
+void mt_pll_raise_little_cpu_freq(u32 freq)
+{
+	/* enable [4] intermediate clock armpll_divider_pll1_ck */
+	setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4);
+
+	/* switch ca55 clock source to intermediate clock */
+	clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_DIV_PLL1);
+
+	/* disable armpll_ll frequency output */
+	clrbits32(plls[APMIXED_ARMPLL_LL].reg, PLL_EN);
+
+	/* raise armpll_ll frequency */
+	pll_set_rate(&plls[APMIXED_ARMPLL_LL], freq);
+
+	/* enable armpll_ll frequency output */
+	setbits32(plls[APMIXED_ARMPLL_LL].reg, PLL_EN);
+	udelay(PLL_EN_DELAY);
+
+	/* switch ca55 clock source back to armpll_ll */
+	clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
+
+	/* disable [4] intermediate clock armpll_divider_pll1_ck */
+	clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4);
+}