diff options
Diffstat (limited to 'src/soc/mediatek/mt8192/include')
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/pll.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h index 52bf3c2f38..cd1c01250c 100644 --- a/src/soc/mediatek/mt8192/include/soc/pll.h +++ b/src/soc/mediatek/mt8192/include/soc/pll.h @@ -241,6 +241,8 @@ check_member(mtk_apmixed_regs, ap_pllgp1_con0, 0x0200); check_member(mtk_apmixed_regs, ap_pllgp2_con0, 0x0300); check_member(mtk_apmixed_regs, usbpll_con2, 0x03cc); +#define MPLL_CON1_FREQ 0x84200000 + enum { USBPLL_EN = 0x1 << 2, @@ -306,6 +308,12 @@ DEFINE_BITFIELD(CLK_MISC_CFG_0_METER_DIV, 31, 24) DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4) DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16) +DEFINE_BIT(MPLL_IOS_SEL, 2) +DEFINE_BIT(MPLL_EN_SEL, 11) +DEFINE_BIT(MPLL_PWR_SEL, 20) +DEFINE_BIT(MPLL_BY_ISO_DLY, 2) +DEFINE_BIT(MPLL_BY_PWR_DLY, 2) + DEFINE_BITFIELD(WDT_SWSYSRST_KEY, 31, 24) DEFINE_BITFIELD(WDT_SWSYSRST_CONN_MCU, 12, 12) |