diff options
Diffstat (limited to 'src/soc/mediatek/mt8188')
| -rw-r--r-- | src/soc/mediatek/mt8188/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8188/bootblock.c | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8188/include/soc/addressmap.h | 5 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8188/include/soc/infracfg.h | 427 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8188/include/soc/mcucfg.h | 969 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8188/include/soc/pll.h | 397 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8188/include/soc/spm.h | 958 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8188/pll.c | 720 |
8 files changed, 3478 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8188/Makefile.inc b/src/soc/mediatek/mt8188/Makefile.inc index 100dde2377..8b50003d8d 100644 --- a/src/soc/mediatek/mt8188/Makefile.inc +++ b/src/soc/mediatek/mt8188/Makefile.inc @@ -3,6 +3,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8188),y) all-y += ../common/flash_controller.c all-y += ../common/gpio.c ../common/gpio_op.c gpio.c all-y += ../common/i2c.c i2c.c +all-y += ../common/pll.c pll.c all-$(CONFIG_SPI_FLASH) += spi.c all-y += ../common/timer.c ../common/timer_prepare.c all-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8188/bootblock.c b/src/soc/mediatek/mt8188/bootblock.c index 770c6031da..8dffe5671b 100644 --- a/src/soc/mediatek/mt8188/bootblock.c +++ b/src/soc/mediatek/mt8188/bootblock.c @@ -2,10 +2,12 @@ #include <bootblock_common.h> #include <soc/mmu_operations.h> +#include <soc/pll.h> #include <soc/wdt.h> void bootblock_soc_init(void) { mtk_mmu_init(); mtk_wdt_init(); + mt_pll_init(); } diff --git a/src/soc/mediatek/mt8188/include/soc/addressmap.h b/src/soc/mediatek/mt8188/include/soc/addressmap.h index d198dd7f47..7e3f9c00cf 100644 --- a/src/soc/mediatek/mt8188/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8188/include/soc/addressmap.h @@ -15,12 +15,15 @@ enum { enum { CKSYS_BASE = IO_PHYS + 0x00000000, + INFRACFG_AO_BASE = IO_PHYS + 0x00001000, GPIO_BASE = IO_PHYS + 0x00005000, SPM_BASE = IO_PHYS + 0x00006000, RGU_BASE = IO_PHYS + 0x00007000, GPT_BASE = IO_PHYS + 0x00008000, EINT_BASE = IO_PHYS + 0x0000B000, + APMIXED_BASE = IO_PHYS + 0x0000C000, SYSTIMER_BASE = IO_PHYS + 0x00017000, + INFRACFG_AO_BCRM_BASE = IO_PHYS + 0x00022000, PMIF_SPI_BASE = IO_PHYS + 0x00024000, PMICSPI_MST_BASE = IO_PHYS + 0x00025000, PMIF_SPMI_BASE = IO_PHYS + 0x00027000, @@ -34,6 +37,7 @@ enum { I2C4_DMA_BASE = IO_PHYS + 0x00220380, I2C5_DMA_BASE = IO_PHYS + 0x00220480, I2C6_DMA_BASE = IO_PHYS + 0x00220600, + SCP_ADSP_CFG_BASE = IO_PHYS + 0x00720000, DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, DPM_PM_SRAM_BASE = IO_PHYS + 0x00900000, DPM_DM_SRAM_BASE = IO_PHYS + 0x00920000, @@ -46,6 +50,7 @@ enum { UART2_BASE = IO_PHYS + 0x01001300, UART3_BASE = IO_PHYS + 0x01001400, AUXADC_BASE = IO_PHYS + 0x01002000, + PERICFG_AO_BASE = IO_PHYS + 0x01003000, SPI0_BASE = IO_PHYS + 0x0100A000, SPI1_BASE = IO_PHYS + 0x01010000, SPI2_BASE = IO_PHYS + 0x01012000, diff --git a/src/soc/mediatek/mt8188/include/soc/infracfg.h b/src/soc/mediatek/mt8188/include/soc/infracfg.h new file mode 100644 index 0000000000..e35c637413 --- /dev/null +++ b/src/soc/mediatek/mt8188/include/soc/infracfg.h @@ -0,0 +1,427 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8188_INFRACFG_H +#define SOC_MEDIATEK_MT8188_INFRACFG_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8188_infracfg_ao_regs { + u8 reserved0[80]; + u32 infra_globalcon_dcmctl; + u8 reserved1[28]; + u32 infra_bus_dcm_ctrl; + u32 peri_bus_dcm_ctrl; + u32 mem_dcm_ctrl; + u32 dfs_mem_dcm_ctrl; + u32 module_sw_cg_0_set; + u32 module_sw_cg_0_clr; + u32 module_sw_cg_1_set; + u32 module_sw_cg_1_clr; + u32 module_sw_cg_0_sta; + u32 module_sw_cg_1_sta; + u32 module_clk_sel; + u32 mem_cg_ctrl; + u32 p2p_rx_clk_on; + u32 module_sw_cg_2_set; + u32 module_sw_cg_2_clr; + u32 module_sw_cg_2_sta; + u8 reserved2[4]; + u32 dramc_wbr; + u8 reserved3[8]; + u32 module_sw_cg_3_set; + u32 module_sw_cg_3_clr; + u32 module_sw_cg_3_sta; + u8 reserved4[20]; + u32 module_sw_cg_4_set; + u32 module_sw_cg_4_clr; + u32 module_sw_cg_4_sta; + u8 reserved5[20]; + u32 i2c_dbtool_misc; + u32 md_sleep_ctrl_mask; + u32 pmicw_clock_ctrl; + u8 reserved6[20]; + u32 infra_globalcon_rst0_set; + u32 infra_globalcon_rst0_clr; + u32 infra_globalcon_rst0_sta; + u8 reserved7[4]; + u32 infra_globalcon_rst1_set; + u32 infra_globalcon_rst1_clr; + u32 infra_globalcon_rst1_sta; + u8 reserved8[4]; + u32 infra_globalcon_rst2_set; + u32 infra_globalcon_rst2_clr; + u32 infra_globalcon_rst2_sta; + u8 reserved9[4]; + u32 infra_globalcon_rst3_set; + u32 infra_globalcon_rst3_clr; + u32 infra_globalcon_rst3_sta; + u8 reserved10[164]; + u32 infra_topaxi_si0_ctl; + u32 infra_topaxi_si1_ctl; + u32 infra_topaxi_mdbus_ctl; + u32 infra_mci_si0_ctl; + u32 infra_mci_si1_ctl; + u32 infra_mci_si2_ctl; + u32 infra_mci_async_ctl; + u32 infra_mci_cg_mfg_sec_sta; + u32 infra_topaxi_protecten; + u32 infra_topaxi_protecten_sta0; + u32 infra_topaxi_protecten_sta1; + u8 reserved11[4]; + u32 infra_apb_async_sta; + u32 infra_topaxi_si2_ctl; + u32 infra_topaxi_fmem_mdhw_ctrl; + u32 infra_conn_gals_ctl; + u32 infra_mci_trans_con_read; + u32 infra_mci_trans_con_write; + u32 infra_mci_id_remap_con; + u32 infra_mci_emi_trans_con; + u32 infra_topaxi_protecten_1; + u32 infra_topaxi_protecten_sta0_1; + u32 infra_topaxi_protecten_sta1_1; + u8 reserved12[4]; + u32 infra_topaxi_aslice_ctrl; + u32 infra_topaxi_aslice_ctrl_1; + u32 infra_topaxi_aslice_ctrl_2; + u32 infra_topaxi_aslice_ctrl_3; + u32 infra_topaxi_mi_ctrl; + u32 infra_topaxi_cbip_aslice_ctrl; + u32 infra_topaxi_cbip_slice_ctrl; + u32 infra_top_master_sideband; + u32 infra_ssusb_dev; + u8 reserved13[4]; + u32 infra_topaxi_emi_gmc_l2c_ctrl; + u32 infra_topaxi_cbip_slice_ctrl_1; + u32 infra_mfg_slave_gals_ctrl; + u32 infra_mfg_master_m0_gals_ctrl; + u32 infra_mfg_master_m1_gals_ctrl; + u32 infra_top_master_sideband_1; + u32 infra_topaxi_protecten_set; + u32 infra_topaxi_protecten_clr; + u32 infra_topaxi_protecten_1_set; + u32 infra_topaxi_protecten_1_clr; + u32 infra_topaxi_cbip_slice_ctrl_2; + u8 reserved14[4]; + u32 infra_topaxi_aslice_ctrl_4; + u8 reserved15[4]; + u32 infra_topaxi_protecten_mcu; + u32 infra_topaxi_protecten_mcu_set; + u32 infra_topaxi_protecten_mcu_clr; + u8 reserved16[4]; + u32 infra_topaxi_protecten_mm; + u32 infra_topaxi_protecten_mm_set; + u32 infra_topaxi_protecten_mm_clr; + u8 reserved17[4]; + u32 infra_topaxi_protecten_mcu_sta0; + u32 infra_topaxi_protecten_mcu_sta1; + u32 infra_topaxi_protecten_mm_sta0; + u32 infra_topaxi_protecten_mm_sta1; + u8 reserved18[4]; + u32 infra_apu_master_m0_gals_ctl; + u32 infra_apu_master_m1_gals_ctl; + u32 infra_topaxi_bus_dbg_con_ao; + u32 md1_bank0_map0; + u32 md1_bank0_map1; + u32 md1_bank0_map2; + u32 md1_bank0_map3; + u32 md1_bank1_map0; + u32 md1_bank1_map1; + u32 md1_bank1_map2; + u32 md1_bank1_map3; + u32 md1_bank4_map0; + u32 md1_bank4_map1; + u32 md1_bank4_map2; + u32 md1_bank4_map3; + u32 md2_bank0_map0; + u32 md2_bank0_map1; + u32 md2_bank0_map2; + u32 md2_bank0_map3; + u8 reserved19[16]; + u32 md2_bank4_map0; + u32 md2_bank4_map1; + u32 md2_bank4_map2; + u32 md2_bank4_map3; + u32 c2k_config; + u32 c2k_status; + u32 c2k_spm_ctrl; + u8 reserved20[4]; + u32 ap2md_dummy; + u8 reserved21[12]; + u32 conn_map0; + u32 cldma_map0; + u32 conn_map1; + u32 conn_bus_con; + u32 mcusys_dfd_map; + u32 conn_map2; + u32 conn_map3; + u32 conn_map4; + u32 module_clk_sel_set; + u32 module_clk_sel_clr; + u32 pmicw_clock_ctrl_set; + u32 pmicw_clock_ctrl_clr; + u32 dramc_wbr_set; + u32 dramc_wbr_clr; + u32 topaxi_si0_ctl_set; + u32 topaxi_si0_ctl_clr; + u32 topaxi_si1_ctl_set; + u32 topaxi_si1_ctl_clr; + u8 reserved22[56]; + u32 peri_cci_sideband_con; + u32 mfg_cci_sideband_con; + u8 reserved23[8]; + u32 infra_pwm_cksw_ctrl; + u8 reserved24[236]; + u32 infra_ao_dbg_con0; + u32 infra_ao_dbg_con1; + u32 infra_ao_dbg_con2; + u32 infra_ao_dbg_con3; + u32 md_dbg_ck_con; + u32 infra_ao_dbg_sta; + u8 reserved25[232]; + u32 mfg_misc_con; + u8 reserved26[12]; + u32 infracfg_ao_iommu_0; + u32 infracfg_ao_iommu_1; + u8 reserved27[228]; + u32 infra_msdc_con; + u32 infra_rsvd0; + u32 infra_rsvd1; + u32 infra_rsvd2; + u32 infra_rsvd3; + u32 infra_topaxi_protecten_2; + u32 infra_topaxi_protecten_set_2; + u32 infra_topaxi_protecten_clr_2; + u8 reserved28[4]; + u32 infra_topaxi_protecten_sta0_2; + u32 infra_topaxi_protecten_sta1_2; + u8 reserved29[8]; + u32 infra_globalcon_rst4_set; + u32 infra_globalcon_rst4_clr; + u32 infra_globalcon_rst4_sta; + u32 infra_ao_sec_rst_con4; + u32 vdnr_con0; + u32 vdnr_con1; + u32 vdnr_con2; + u32 vdnr_con3; + u8 reserved30[48]; + u32 mcu2emi_m0_parity; + u32 mcu2emi_m0_parity_dbg_aw_1; + u32 mcu2emi_m0_parity_dbg_aw_2; + u32 mcu2emi_m0_parity_dbg_ar_1; + u32 mcu2emi_m0_parity_dbg_ar_2; + u32 mcu2emi_m1_parity; + u32 mcu2emi_m1_parity_dbg_aw_1; + u32 mcu2emi_m1_parity_dbg_aw_2; + u32 mcu2emi_m1_parity_dbg_ar_1; + u32 mcu2emi_m1_parity_dbg_ar_2; + u32 mcu2ifr_reg_parity; + u32 mcu2ifr_reg_parity_dbg_aw_1; + u32 mcu2ifr_reg_parity_dbg_aw_2; + u32 mcu2ifr_reg_parity_dbg_ar_1; + u32 mcu2ifr_reg_parity_dbg_ar_2; + u32 ifr_l3c2mcu_parity; + u32 ifr_l3c2mcu_parity_dbg_r_1; + u8 reserved31[108]; + u32 gcpu_aor_ctrl; + u32 gcpu_aor_lock_sbc_pubk_hv; + u8 reserved32[8]; + u32 gcpu_aor_sbc_pubk_hv0; + u32 gcpu_aor_sbc_pubk_hv1; + u32 gcpu_aor_sbc_pubk_hv2; + u32 gcpu_aor_sbc_pubk_hv3; + u32 gcpu_aor_sbc_pubk_hv4; + u32 gcpu_aor_sbc_pubk_hv5; + u32 gcpu_aor_sbc_pubk_hv6; + u32 gcpu_aor_sbc_pubk_hv7; + u32 gcpu_aor_sbc_pubk_hv8; + u32 gcpu_aor_sbc_pubk_hv9; + u32 gcpu_aor_sbc_pubk_hv10; + u32 gcpu_aor_sbc_pubk_hv11; + u8 reserved33[144]; + u32 infra_bonding; + u8 reserved34[252]; + u32 infra_ao_scpsys_apb_async_sta; + u32 infra_ao_md32_tx_apb_async_sta; + u32 infra_ao_md32_rx_apb_async_sta; + u32 infra_ao_cksys_apb_async_sta; + u32 infra_ao_pmic_wrap_tx_apb_async_sta; + u32 infra_mcu2apu_asl0_ctl; + u32 infra_mcu2reg_asl0_ctl; + u32 infra_mcu_decoder_infra_ctl; + u32 infra_mcu_decoder_sta0; + u32 infra_mcu_decoder_sta1; + u32 infra_idle_async_bit_en_0; + u32 infra_apu_slave_gals_ctrl; + u32 infra_aximem_idle_bit_en_0; + u32 infra_mcu_path_sync_ctl; + u32 infra_conn2ap_int_mask; + u32 infra_mcu_pwr_ctl_mask; + u32 infra_md_rsv; + u8 reserved35[28]; + u32 infra_mem_26m_cksel; + u8 reserved36[28]; + u32 infra_tinsys_master_m1_gals_ctrl; + u32 infra_tinsys_master_m0_gals_ctrl; + u32 infra_nna2adsp_slave_gals_ctrl; + u32 infra_tinsys_slave_gals_ctrl; + u32 infra_apu2adsp_master_gals_ctrl; + u32 mfg2infra_gals_ctrl; + u8 reserved37[104]; + u32 pll_ulposc_con0; + u32 pll_ulposc_con1; + u8 reserved38[8]; + u32 pll_auxadc_con0; + u32 scp_infra_irq_set; + u32 scp_infra_irq_clr; + u32 scp_infra_ctrl; + u8 reserved39[96]; + u32 infra_topaxi_protecten_vdnr; + u32 infra_topaxi_protecten_vdnr_set; + u32 infra_topaxi_protecten_vdnr_clr; + u32 infra_topaxi_protecten_vdnr_sta0; + u32 infra_topaxi_protecten_vdnr_sta1; + u8 reserved40[12]; + u32 infra_topaxi_protecten_vdnr_1; + u32 infra_topaxi_protecten_vdnr_set_1; + u32 infra_topaxi_protecten_vdnr_clr_1; + u32 infra_topaxi_protecten_vdnr_sta0_1; + u32 infra_topaxi_protecten_vdnr_sta1_1; + u32 infra_topaxi_protecten_vdnr_2; + u32 infra_topaxi_protecten_vdnr_set_2; + u32 infra_topaxi_protecten_vdnr_clr_2; + u32 infra_topaxi_protecten_vdnr_sta0_2; + u32 infra_topaxi_protecten_vdnr_sta1_2; + u32 infra_topaxi_protecten_sub_infra_vdnr; + u32 infra_topaxi_protecten_sub_infra_vdnr_set; + u32 infra_topaxi_protecten_sub_infra_vdnr_clr; + u32 infra_topaxi_protecten_sub_infra_vdnr_sta0; + u32 infra_topaxi_protecten_sub_infra_vdnr_sta1; + u8 reserved41[36]; + u32 cldma_ctrl; + u8 reserved42[252]; + u32 infrabus_dbg0; + u32 infrabus_dbg1; + u32 infrabus_dbg2; + u32 infrabus_dbg3; + u32 infrabus_dbg4; + u32 infrabus_dbg5; + u32 infrabus_dbg6; + u32 infrabus_dbg7; + u32 infrabus_dbg8; + u32 infrabus_dbg9; + u32 infrabus_dbg10; + u32 infrabus_dbg11; + u32 infrabus_dbg12; + u32 infrabus_dbg13; + u32 infrabus_dbg14; + u32 infrabus_dbg15; + u32 infrabus_dbg16; + u32 infrabus_dbg17; + u32 infrabus_dbg18; + u32 infrabus_dbg19; + u32 infrabus_dbg20; + u32 infrabus_dbg21; + u32 infrabus_dbg22; + u32 infrabus_dbg23; + u32 infrabus_dbg24; + u32 infrabus_dbg25; + u32 infrabus_dbg26; + u32 infrabus_dbg27; + u32 infrabus_dbg28; + u32 infrabus_dbg29; + u32 infrabus_dbg30; + u32 infrabus_dbg31; + u32 infrabus_dbg32; + u32 infrabus_dbg33; + u32 infrabus_dbg34; + u32 infrabus_dbg35; + u32 infrabus_dbg36; + u32 infrabus_dbg37; + u32 infrabus_dbg38; + u32 infrabus_dbg39; + u32 infrabus_dbg40; + u32 infrabus_dbg41; + u32 infrabus_dbg42; + u32 infrabus_dbg43; + u32 infrabus_dbg44; + u32 infrabus_dbg45; + u8 reserved43[16]; + u32 infra_topaxi_protecten_mm_2; + u32 infra_topaxi_protecten_mm_set_2; + u32 infra_topaxi_protecten_mm_clr_2; + u32 infra_topaxi_protecten_mm_sta0_2; + u32 infra_topaxi_protecten_mm_sta1_2; + u8 reserved44[20]; + u32 infrabus_dbg_mask2; + u8 reserved45[76]; + u32 infra_ao_sec_mm0; + u32 infra_ao_sec_mm1; + u32 infra_ao_sec_mm2; + u32 infra_ao_sec_mm3; + u32 infra_ao_sec_mm4; + u32 infra_ao_sec_mm5; + u32 infra_ao_sec_mm6; + u8 reserved46[164]; + u32 infra_misc; + u32 infra_acp; + u32 misc_config; + u32 infra_misc2; + u32 mdsys_misc_con; + u8 reserved47[108]; + u32 infra_ao_sec_con; + u32 infra_ao_sec_cg_con0; + u32 infra_ao_sec_cg_con1; + u32 infra_ao_sec_rst_con0; + u32 infra_ao_sec_rst_con1; + u32 infra_ao_sec_rst_con2; + u8 reserved48[4]; + u32 infra_ao_sec_cg_con2; + u32 infra_ao_sec_rst_con3; + u32 infra_ao_sec_cg_con3; + u8 reserved49[8]; + u32 infra_ao_sec_hyp; + u32 infra_ao_sec_mfg_hyp; +}; + +check_member(mt8188_infracfg_ao_regs, infra_globalcon_dcmctl, 0x0050); +check_member(mt8188_infracfg_ao_regs, infra_bus_dcm_ctrl, 0x0070); +check_member(mt8188_infracfg_ao_regs, module_sw_cg_0_clr, 0x0084); +check_member(mt8188_infracfg_ao_regs, module_sw_cg_1_clr, 0x008c); +check_member(mt8188_infracfg_ao_regs, module_sw_cg_2_clr, 0x00a8); +check_member(mt8188_infracfg_ao_regs, module_sw_cg_3_set, 0x00c0); +check_member(mt8188_infracfg_ao_regs, module_sw_cg_4_set, 0x00e0); +check_member(mt8188_infracfg_ao_regs, i2c_dbtool_misc, 0x0100); +check_member(mt8188_infracfg_ao_regs, infra_globalcon_rst0_set, 0x0120); +check_member(mt8188_infracfg_ao_regs, md2_bank4_map0, 0x0350); +check_member(mt8188_infracfg_ao_regs, conn_map0, 0x0380); +check_member(mt8188_infracfg_ao_regs, peri_cci_sideband_con, 0x0400); +check_member(mt8188_infracfg_ao_regs, infra_pwm_cksw_ctrl, 0x0410); +check_member(mt8188_infracfg_ao_regs, infra_ao_dbg_con0, 0x0500); +check_member(mt8188_infracfg_ao_regs, mfg_misc_con, 0x0600); +check_member(mt8188_infracfg_ao_regs, infracfg_ao_iommu_0, 0x0610); +check_member(mt8188_infracfg_ao_regs, infra_rsvd0, 0x0700); +check_member(mt8188_infracfg_ao_regs, infra_globalcon_rst4_set, 0x0730); +check_member(mt8188_infracfg_ao_regs, mcu2emi_m0_parity, 0x0780); +check_member(mt8188_infracfg_ao_regs, gcpu_aor_ctrl, 0x0830); +check_member(mt8188_infracfg_ao_regs, gcpu_aor_sbc_pubk_hv0, 0x0840); +check_member(mt8188_infracfg_ao_regs, infra_bonding, 0x0900); +check_member(mt8188_infracfg_ao_regs, infra_ao_scpsys_apb_async_sta, 0x0a00); +check_member(mt8188_infracfg_ao_regs, infra_mem_26m_cksel, 0x0a60); +check_member(mt8188_infracfg_ao_regs, pll_ulposc_con0, 0x0b00); +check_member(mt8188_infracfg_ao_regs, pll_auxadc_con0, 0x0b10); +check_member(mt8188_infracfg_ao_regs, infra_topaxi_protecten_vdnr, 0x0b80); +check_member(mt8188_infracfg_ao_regs, infra_topaxi_protecten_vdnr_1, 0x0ba0); +check_member(mt8188_infracfg_ao_regs, cldma_ctrl, 0x0c00); +check_member(mt8188_infracfg_ao_regs, infrabus_dbg0, 0x0d00); +check_member(mt8188_infracfg_ao_regs, infra_topaxi_protecten_mm_2, 0x0dc8); +check_member(mt8188_infracfg_ao_regs, infrabus_dbg_mask2, 0x0df0); +check_member(mt8188_infracfg_ao_regs, infra_misc, 0x0f00); +check_member(mt8188_infracfg_ao_regs, infra_ao_sec_con, 0x0f80); +check_member(mt8188_infracfg_ao_regs, infra_ao_sec_hyp, 0x0fb0); +check_member(mt8188_infracfg_ao_regs, infra_ao_sec_mfg_hyp, 0x0fb4); + +static struct mt8188_infracfg_ao_regs *const mt8188_infracfg_ao = + (void *)INFRACFG_AO_BASE; + +#endif /* SOC_MEDIATEK_MT8188_INFRACFG_H */ diff --git a/src/soc/mediatek/mt8188/include/soc/mcucfg.h b/src/soc/mediatek/mt8188/include/soc/mcucfg.h new file mode 100644 index 0000000000..9bd278eea6 --- /dev/null +++ b/src/soc/mediatek/mt8188/include/soc/mcucfg.h @@ -0,0 +1,969 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8188_MCUCFG_H +#define SOC_MEDIATEK_MT8188_MCUCFG_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8188_mcucfg_regs { + u8 reserved0[8]; + u32 mbista_mcsi_sf1_con; + u32 mbista_mcsi_sf1_result; + u32 mbista_mcsi_sf2_con; + u32 mbista_mcsi_sf2_result; + u32 mbista_etb_con; + u32 mbista_etb_result; + u32 mbista_rstb; + u32 mbista_all_result; + u8 reserved1[8]; + u32 mbist_trigger_mux_ctl; + u8 reserved2[12]; + u32 dfd_ctrl; + u32 dfd_cnt_l; + u32 dfd_cnt_h; + u8 reserved3[20]; + u32 mp_top_dbg_mon_sel; + u32 mp_top_dbg_mon; + u32 mp0_dbg_mon_sel; + u32 mp0_dbg_mon; + u8 reserved4[112]; + u32 mp0_ptp_sensor_sel; + u32 emi_addr_wrap_cfg; + u32 emi_addr_wrap_state; + u8 reserved5[12]; + u32 armpll_jit_clk_out_sel; + u8 reserved6[4]; + u32 cci_tra_cfg0; + u8 reserved7[16]; + u32 cci_tra_cfg5; + u32 cci_tra_cfg6; + u32 cci_tra_cfg7; + u32 cci_tra_cfg8; + u32 cci_tra_cfg9; + u32 cci_tra_cfg10; + u32 cci_tra_cfg11; + u32 cci_tra_cfg12; + u8 reserved8[204]; + u32 cci_m0_tra; + u32 cci_m1_tra; + u32 cci_m2_tra; + u8 reserved9[20]; + u32 cci_s1_tra; + u32 cci_s2_tra; + u32 cci_s3_tra; + u32 cci_s4_tra; + u8 reserved10[16]; + u32 cci_m0_tra_latch; + u32 cci_m1_tra_latch; + u32 cci_m2_tra_latch; + u8 reserved11[20]; + u32 cci_s1_tra_latch; + u32 cci_s2_tra_latch; + u32 cci_s3_tra_latch; + u32 cci_s4_tra_latch; + u8 reserved12[80]; + u32 cci_m0_if; + u32 cci_m1_if; + u32 cci_m2_if; + u8 reserved13[20]; + u32 cci_s1_if; + u32 cci_s2_if; + u32 cci_s3_if; + u32 cci_s4_if; + u8 reserved14[48]; + u32 cci_m0_if_latch; + u32 cci_m1_if_latch; + u32 cci_m2_if_latch; + u8 reserved15[20]; + u32 cci_s1_if_latch; + u32 cci_s2_if_latch; + u32 cci_s3_if_latch; + u32 cci_s4_if_latch; + u8 reserved16[176]; + u32 l3c_share_status0; + u32 l3c_share_status1; + u32 l3c_share_status2; + u8 reserved17[4]; + u32 mp0_cpu0_dc_age; + u32 mp0_cpu1_dc_age; + u32 mp0_cpu2_dc_age; + u32 mp0_cpu3_dc_age; + u32 mp0_cpu4_dc_age; + u32 mp0_cpu5_dc_age; + u32 mp0_cpu6_dc_age; + u32 mp0_cpu7_dc_age; + u8 reserved18[208]; + u32 mp0_cpu0_nonwfx_ctrl; + u32 mp0_cpu0_nonwfx_cnt; + u32 mp0_cpu1_nonwfx_ctrl; + u32 mp0_cpu1_nonwfx_cnt; + u32 mp0_cpu2_nonwfx_ctrl; + u32 mp0_cpu2_nonwfx_cnt; + u32 mp0_cpu3_nonwfx_ctrl; + u32 mp0_cpu3_nonwfx_cnt; + u32 mp0_cpu4_nonwfx_ctrl; + u32 mp0_cpu4_nonwfx_cnt; + u32 mp0_cpu5_nonwfx_ctrl; + u32 mp0_cpu5_nonwfx_cnt; + u32 mp0_cpu6_nonwfx_ctrl; + u32 mp0_cpu6_nonwfx_cnt; + u32 mp0_cpu7_nonwfx_ctrl; + u32 mp0_cpu7_nonwfx_cnt; + u8 reserved19[192]; + u32 mp0_ses_apb_trig; + u32 mp0_ses_clk_en; + u8 reserved20[8]; + u32 wfx_ret_met_dbc_sel; + u8 reserved21[12]; + u32 adb_bist_cfg1; + u32 adb_bist_cfg2_md; + u32 adb_bist_cfg3_go; + u32 adb_bist_done; + u32 adb_bist_pass; + u32 adb_bist_done1; + u8 reserved22[4]; + u32 adb_bist_pass1; + u8 reserved23[192]; + u32 axi2acp_cfg_ctrl; + u32 axi2acp_cfg_mask_id; + u8 reserved24[8]; + u32 axi2acp_ar_def_set; + u8 reserved25[4]; + u32 axi2acp_aw_def_set; + u8 reserved26[4]; + u32 axi2acp_err_addr0; + u32 axi2acp_err_addr1; + u32 axi2acp_err_st; + u32 axi2acp_err_id; + u32 axi2acp_err_irq; + u32 axi2acp_err_dbgout; + u8 reserved27[200]; + u32 mst_ccim0_inject_fault; + u32 mst_ccim0_rec_par; + u32 mst_ccim0_log_rid; + u8 reserved28[4]; + u32 mst_ccim0_log_rd0; + u32 mst_ccim0_log_rd1; + u32 mst_ccim0_log_rd2; + u32 mst_ccim0_log_rd3; + u32 mst_ccim1_inject_fault; + u32 mst_ccim1_rec_par; + u32 mst_ccim1_log_rid; + u8 reserved29[4]; + u32 mst_ccim1_log_rd0; + u32 mst_ccim1_log_rd1; + u32 mst_ccim1_log_rd2; + u32 mst_ccim1_log_rd3; + u32 mst_intaxi_inject_fault; + u32 mst_intaxi_rec_par; + u32 mst_intaxi_log_rid; + u8 reserved30[4]; + u32 mst_intaxi_log_rd0; + u32 mst_intaxi_log_rd1; + u8 reserved31[8]; + u32 slv_1to2_inject_fault; + u32 slv_1to2_rec_par; + u32 slv_1to2_log_awid; + u32 slv_1to2_log_arid; + u32 slv_1to2_log_awa0; + u32 slv_1to2_log_awa1; + u32 slv_1to2_log_ara0; + u32 slv_1to2_log_ara1; + u32 slv_1to2_log_wid; + u8 reserved32[12]; + u32 slv_1to2_log_wd0; + u32 slv_1to2_log_wd1; + u32 slv_1to2_log_wd2; + u32 slv_1to2_log_wd3; + u32 slv_l3c_inject_fault; + u32 slv_l3c_rec_par; + u32 slv_l3c_log_awid; + u32 slv_l3c_log_arid; + u32 slv_l3c_log_awa0; + u32 slv_l3c_log_awa1; + u32 slv_l3c_log_ara0; + u32 slv_l3c_log_ara1; + u32 slv_l3c_log_wid; + u8 reserved33[4]; + u32 slv_l3c_log_wd0; + u32 slv_l3c_log_wd1; + u32 slv_gic_inject_fault; + u32 slv_gic_rec_par; + u32 slv_gic_log_awid; + u32 slv_gic_log_arid; + u32 slv_gic_log_awa0; + u32 slv_gic_log_awa1; + u32 slv_gic_log_ara0; + u32 slv_gic_log_ara1; + u32 slv_gic_log_wid; + u8 reserved34[4]; + u32 slv_gic_log_wd0; + u32 slv_gic_log_wd1; + u8 reserved35[256]; + u32 ildo_vin_big0; + u32 ildo_out_big0; + u32 ildo_ovstck_big0; + u32 ildo_vo2hck_big0; + u32 ildo_mhstck_big0; + u32 ildo_mlstck_big0; + u32 ilod_uvwin_big0; + u32 ilod_ovwin_big0; + u32 ildo_pd_cfg_big0; + u8 reserved36[12]; + u32 ildo_vin_big1; + u32 ildo_out_big1; + u32 ildo_ovstck_big1; + u32 ildo_vo2hck_big1; + u32 ildo_mhstck_big1; + u32 ildo_mlstck_big1; + u32 ilod_uvwin_big1; + u32 ilod_ovwin_big1; + u32 ildo_pd_cfg_big1; + u8 reserved37[12]; + u32 ildo_vin_big2; + u32 ildo_out_big2; + u32 ildo_ovstck_big2; + u32 ildo_vo2hck_big2; + u32 ildo_mhstck_big2; + u32 ildo_mlstck_big2; + u32 ilod_uvwin_big2; + u32 ilod_ovwin_big2; + u32 ildo_pd_cfg_big2; + u8 reserved38[12]; + u32 ildo_vin_big3; + u32 ildo_out_big3; + u32 ildo_ovstck_big3; + u32 ildo_vo2hck_big3; + u32 ildo_mhstck_big3; + u32 ildo_mlstck_big3; + u32 ilod_uvwin_big3; + u32 ilod_ovwin_big3; + u32 ildo_pd_cfg_big3; + u8 reserved39[5980]; + u32 l3c_share_cfg0; + u32 l3c_share_cfg1; + u32 l3c_share_cfg2; + u8 reserved40[4]; + u32 udi_cfg0; + u32 udi_cfg1; + u8 reserved41[8]; + u32 mcusys_core_status; + u8 reserved42[4]; + u32 cfg_sys_valid; + u32 cfg_sysbase_addr_0; + u32 cfg_sysbase_addr_1; + u32 cfg_sysbase_addr_2; + u32 cfg_sysbase_addr_3; + u32 cfg_sysbase_addr_4; + u8 reserved43[16]; + u32 mcusys_base; + u32 l3c_sram_base; + u32 gic_periph_base; + u32 cci_periph_base; + u32 cci_periph_infra_base; + u32 dfd_sram_base; + u32 l3c_mm_sram_base; + u32 ext_l3c_sram_base; + u32 ext_gic_periph_base; + u32 mcusys_qos_shaper_degree; + u32 mcusys_qos_shaper_others; + u32 mcusys_qos_age_set_enable; + u32 sspm_cpueb_turbo_pll_ctl; + u32 cpu_eb_apb_base; + u32 cpu_eb_tcm_btb_delsel; + u32 cpu_eb_mem_misc; + u32 cpu_plldiv_cfg0; + u32 cpu_plldiv_cfg1; + u8 reserved44[56]; + u32 bus_plldiv_cfg; + u8 reserved45[12]; + u32 plldiv_ctl0; + u32 cpuplldiv_unictl; + u8 reserved46[8]; + u32 mcsi_ram_delsel0; + u32 mcsi_ram_delsel1; + u8 reserved47[28]; + u32 mbist_delsel_fuse_dis; + u32 mbist_delsel_magic_key; + u8 reserved48[84]; + u32 etb_cfg0; + u8 reserved49[12]; + u32 bus_parity_gen_en; + u32 bus_parity_clr; + u32 bus_parity_chk_en; + u32 bus_parity_fail; + u32 dsu2biu_addr_remap_cfg; + u32 dsu2biu_addr_remap_sta; + u8 reserved50[8]; + u32 dsu2biu_addr_remap_0_cfg0; + u32 dsu2biu_addr_remap_0_cfg1; + u32 dsu2biu_addr_remap_0_cfg2; + u8 reserved51[4]; + u32 dsu2biu_addr_remap_1_cfg0; + u32 dsu2biu_addr_remap_1_cfg1; + u32 dsu2biu_addr_remap_1_cfg2; + u8 reserved52[4]; + u32 dsu2biu_addr_remap_magic; + u8 reserved53[44]; + u32 cci_rgu; + u8 reserved54[12]; + u32 mcsi_cfg0; + u32 mcsi_cfg1; + u32 mcsi_cfg2; + u32 mcsi_cfg3; + u32 mcsi_cfg4; + u8 reserved55[28]; + u32 mcsic_dcm0; + u32 mcsic_dcm1; + u8 reserved56[72]; + u32 apmcu2emi_early_cke_ctl0; + u32 apmcu2emi_early_cke_ctl1; + u32 apmcu2emi_early_ebg01_ctl0; + u32 apmcu2emi_early_ebg01_ctl1; + u32 apmcu2emi_early_ebg01_ctl2; + u32 apmcu2emi_early_ebg01_ctl3; + u8 reserved57[8]; + u32 apmcu2emi_early_ebg_enable01; + u32 apmcu2emi_early_ebg_enable23; + u32 emi_hash_violation; + u32 emi_interleave_update_mask; + u32 apmcu2emi_early_ebg23_ctl0; + u32 apmcu2emi_early_ebg23_ctl1; + u32 apmcu2emi_early_ebg23_ctl2; + u32 apmcu2emi_early_ebg23_ctl3; + u8 reserved58[48]; + u32 mp_adb_dcm_cfg0; + u8 reserved59[4]; + u32 mp_adb_dcm_cfg2; + u8 reserved60[4]; + u32 mp_adb_dcm_cfg4; + u8 reserved61[4]; + u32 mp_misc_dcm_cfg0; + u8 reserved62[36]; + u32 etb_ck_ctl; + u8 reserved63[60]; + u32 dcc_cpu_con0; + u32 dcc_cpu_con1; + u8 reserved64[24]; + u32 dcc_bus_con0; + u8 reserved65[28]; + u32 mcusys_dcm_cfg0; + u8 reserved66[316]; + u32 fcm_spmc_sw_cfg1; + u32 fcm_spmc_sw_cfg2; + u32 fcm_spmc_wait_cfg; + u32 fcm_spmc_sw_pchannel; + u32 fcm_spmc_pwr_status; + u32 fcm_spmc_off_thres; + u32 fcm_spmc_wdt_latch_info; + u8 reserved67[36]; + u32 mcusys_spmc_sw_cfg; + u32 mcusys_spmc_wait_cfg; + u32 mcusys_spmc_pwr_status; + u8 reserved68[180]; + u32 cpc_pllbuck_req_ctrl; + u32 mcusys_pwr_ctrl; + u32 cpusys_pwr_ctrl; + u32 sw_gic_wakeup_req; + u32 cpc_pllbuck_arb_weight; + u32 cpc_flow_ctrl_cfg; + u32 cpc_last_core_req; + u32 cpc_cpusys_last_core_resp; + u8 reserved69[4]; + u32 cpc_mcusys_last_core_resp; + u32 cpc_pwr_on_mask; + u8 reserved70[20]; + u32 cpc_spmc_pwr_status; + u32 cpc_core_cur_fsm; + u32 cpc_cpusys_mcusys_cur_fsm; + u32 cpc_wakeup_req; + u8 reserved71[4]; + u32 cpc_gp0_gp1_status; + u8 reserved72[4]; + u32 cpc_turbo_ctrl; + u32 cpc_turbo_gp0_ctrl; + u32 cpc_turbo_gp1_ctrl; + u32 cpc_turbo_gp2_ctrl; + u32 cpc_turbo_pwr_on_mask; + u32 cpc_turbo_gp0_req; + u32 cpc_turbo_gp1_req; + u32 cpc_turbo_gp2_req; + u8 reserved73[4]; + u32 cpc_turbo_gp0_resp; + u32 cpc_turbo_gp1_resp; + u32 cpc_turbo_gp2_resp; + u32 cpc_coh_block_thres; + u32 cpc_int_status; + u32 cpc_int_enable; + u32 pllbuck_group_func; + u32 cpc_dcm_enable; + u32 cpc_pllbuck_state; + u32 cpc_cpu_on_sw_hint; + u32 cpc_cpu_on_sw_hint_set; + u32 cpc_cpu_on_sw_hint_clear; + u8 reserved74[80]; + u32 emi_wfifo; + u32 axi1to4_cfg; + u32 apb_cfg; + u32 emi_adb_edge_sel; + u8 reserved75[16]; + u32 sclk_cfg_slow_down_ck; + u8 reserved76[12]; + u32 acpwakeup; + u8 reserved77[4]; + u32 l3gic_idle_bypass; + u8 reserved78[84]; + u32 mcusys_dbg_mon_sel; + u32 mcusys_dbg_mon; + u8 reserved79[108]; + u32 lkg_mon_sw; + u32 lkg_mon_en; + u8 reserved80[116]; + u32 gic_acao_ctl0; + u8 reserved81[4]; + u32 gic_acao_ctl2; + u8 reserved82[116]; + u32 spmc_dbg_setting; + u32 kernel_base_l; + u32 kernel_base_h; + u32 systime_base_l; + u32 systime_base_h; + u32 trace_data_selection; + u8 reserved83[8]; + u32 trace_data_entry0_l; + u32 trace_data_entry0_h; + u32 trace_data_entry1_l; + u32 trace_data_entry1_h; + u32 trace_data_entry2_l; + u32 trace_data_entry2_h; + u32 trace_data_entry3_l; + u32 trace_data_entry3_h; + u32 cpu0_on_off_latency; + u32 cpu1_on_off_latency; + u32 cpu2_on_off_latency; + u32 cpu3_on_off_latency; + u32 cpu4_on_off_latency; + u32 cpu5_on_off_latency; + u32 cpu6_on_off_latency; + u32 cpu7_on_off_latency; + u32 cluster_off_latency; + u32 cluster_on_latency; + u32 mcusys_on_off_latency; + u8 reserved84[4]; + u32 cluster_off_dormant_counter; + u32 cluster_off_dormant_counter_clear; + u32 turbo_gp0_gp1_latency; + u32 turbo_gp2_latency; + u32 cpc_wdt_latch_info1; + u32 cpc_wdt_latch_info2; + u32 cpc_wdt_latch_info3; + u32 cpc_wdt_latch_info4; + u32 cpc_wdt_latch_info5; + u32 cpc_pmu_ctrl; + u32 cpc_pmu_cnt_clr; + u32 cpc_pmu_cnt0; + u8 reserved85[16]; + u32 cpc_wdt_latch_info6; + u32 cpc_wdt_latch_info7; + u32 cpc_ptm_event_en_ctrl; + u32 cpc_ptm_event_en_ctrl1; + u32 cpc_ptm_trace_sel; + u32 cpc_ptm_trace_status_l; + u32 cpc_ptm_trace_status_h; + u8 reserved86[116]; + u32 sesv6_bg_ctrl; + u8 reserved87[12]; + u32 dsu_sesv6_ao_reg0; + u32 dsu_sesv6_ao_reg1; + u32 dsu_sesv6_ao_reg2; + u32 dsu_sesv6_ao_reg3; + u32 dsu_sesv6_ao_reg4; + u8 reserved88[156]; + u32 ildo_dout_sel; + u8 reserved89[124]; + u32 dreq20_little_en; + u8 reserved90[8]; + u32 dreq20_big_vproc_iso; + u8 reserved91[112]; + u32 pikachu_event; + u32 pikachu_status; + u8 reserved92[504]; + u32 cpu0_drcc_ao_config; + u8 reserved93[12]; + u32 cpu0_sesv6_ao_reg0; + u32 cpu0_sesv6_ao_reg1; + u32 cpu0_sesv6_ao_reg2; + u32 cpu0_sesv6_ao_reg3; + u32 cpu0_sesv6_ao_reg4; + u8 reserved94[28]; + u32 cpu0_dfs_cfg; + u8 reserved95[12]; + u32 cpu0_turbo_cfg; + u8 reserved96[420]; + u32 cpu0_resereved_reg; + u32 cpu0_resereved_reg_rd; + u32 cpu1_drcc_ao_config; + u8 reserved97[12]; + u32 cpu1_sesv6_ao_reg0; + u32 cpu1_sesv6_ao_reg1; + u32 cpu1_sesv6_ao_reg2; + u32 cpu1_sesv6_ao_reg3; + u32 cpu1_sesv6_ao_reg4; + u8 reserved98[28]; + u32 cpu1_dfs_cfg; + u8 reserved99[12]; + u32 cpu1_turbo_cfg; + u8 reserved100[420]; + u32 cpu1_resereved_reg; + u32 cpu1_resereved_reg_rd; + u32 cpu2_drcc_ao_config; + u8 reserved101[12]; + u32 cpu2_sesv6_ao_reg0; + u32 cpu2_sesv6_ao_reg1; + u32 cpu2_sesv6_ao_reg2; + u32 cpu2_sesv6_ao_reg3; + u32 cpu2_sesv6_ao_reg4; + u8 reserved102[28]; + u32 cpu2_dfs_cfg; + u8 reserved103[12]; + u32 cpu2_turbo_cfg; + u8 reserved104[420]; + u32 cpu2_resereved_reg; + u32 cpu2_resereved_reg_rd; + u32 cpu3_drcc_ao_config; + u8 reserved105[12]; + u32 cpu3_sesv6_ao_reg0; + u32 cpu3_sesv6_ao_reg1; + u32 cpu3_sesv6_ao_reg2; + u32 cpu3_sesv6_ao_reg3; + u32 cpu3_sesv6_ao_reg4; + u8 reserved106[28]; + u32 cpu3_dfs_cfg; + u8 reserved107[12]; + u32 cpu3_turbo_cfg; + u8 reserved108[420]; + u32 cpu3_resereved_reg; + u32 cpu3_resereved_reg_rd; + u32 cpu4_drcc_ao_config; + u8 reserved109[12]; + u32 cpu4_sesv6_ao_reg0; + u32 cpu4_sesv6_ao_reg1; + u32 cpu4_sesv6_ao_reg2; + u32 cpu4_sesv6_ao_reg3; + u32 cpu4_sesv6_ao_reg4; + u8 reserved110[28]; + u32 cpu4_dfs_cfg; + u8 reserved111[12]; + u32 cpu4_turbo_cfg; + u8 reserved112[420]; + u32 cpu4_resereved_reg; + u32 cpu4_resereved_reg_rd; + u32 cpu5_drcc_ao_config; + u8 reserved113[12]; + u32 cpu5_sesv6_ao_reg0; + u32 cpu5_sesv6_ao_reg1; + u32 cpu5_sesv6_ao_reg2; + u32 cpu5_sesv6_ao_reg3; + u32 cpu5_sesv6_ao_reg4; + u8 reserved114[28]; + u32 cpu5_dfs_cfg; + u8 reserved115[12]; + u32 cpu5_turbo_cfg; + u8 reserved116[420]; + u32 cpu5_resereved_reg; + u32 cpu5_resereved_reg_rd; + u32 cpu6_drcc_ao_config; + u8 reserved117[12]; + u32 cpu6_sesv6_ao_reg0; + u32 cpu6_sesv6_ao_reg1; + u32 cpu6_sesv6_ao_reg2; + u32 cpu6_sesv6_ao_reg3; + u32 cpu6_sesv6_ao_reg4; + u8 reserved118[12]; + u32 cpu6_didt_reg; + u32 cpu6_mem_lre_reg; + u8 reserved119[8]; + u32 cpu6_dfs_cfg; + u8 reserved120[12]; + u32 cpu6_turbo_cfg; + u8 reserved121[420]; + u32 cpu6_resereved_reg; + u32 cpu6_resereved_reg_rd; + u32 cpu7_drcc_ao_config; + u8 reserved122[12]; + u32 cpu7_sesv6_ao_reg0; + u32 cpu7_sesv6_ao_reg1; + u32 cpu7_sesv6_ao_reg2; + u32 cpu7_sesv6_ao_reg3; + u32 cpu7_sesv6_ao_reg4; + u8 reserved123[12]; + u32 cpu7_didt_reg; + u32 cpu7_mem_lre_reg; + u8 reserved124[8]; + u32 cpu7_dfs_cfg; + u8 reserved125[12]; + u32 cpu7_turbo_cfg; + u8 reserved126[420]; + u32 cpu7_resereved_reg; + u32 cpu7_resereved_reg_rd; + u8 reserved127[2048]; + u32 mp0_mbist_cfg; + u8 reserved128[60]; + u32 mp0_l3_data_ram_delsel; + u32 mp0_l3_tag_ram_delsel; + u32 mp0_l3_victim_ram_delsel; + u32 mp0_l3_scu_sf_ram_delsel; + u8 reserved129[48]; + u32 mp0_dcm_cfg0; + u32 mp0_dcm_cfg1; + u32 mp0_dcm_cfg2; + u32 mp0_dcm_cfg3; + u32 mp0_dcm_cfg4; + u32 mp0_dcm_cfg5; + u32 mp0_dcm_cfg6; + u32 mp0_dcm_cfg7; + u32 mp0_dcm_cfg8; + u8 reserved130[28]; + u32 mp0_l3_cache_parity1; + u32 mp0_l3_cache_parity2; + u32 mp0_l3_cache_parity3; + u8 reserved131[4]; + u32 mp0_cluster_cfg0; + u8 reserved132[12]; + u32 mp0_cluster_cfg4; + u32 mp0_cluster_cfg5; + u32 mp0_cluster_cfg6; + u32 mp0_cluster_cfg7; + u8 reserved133[16]; + u32 mp0_cluster_cfg8; + u32 mp0_cluster_cfg9; + u32 mp0_cluster_cfg10; + u32 mp0_cluster_cfg11; + u32 mp0_cluster_cfg12; + u32 mp0_cluster_cfg13; + u32 mp0_cluster_cfg14; + u32 mp0_cluster_cfg15; + u32 mp0_cluster_cfg16; + u32 mp0_cluster_cfg17; + u32 mp0_cluster_cfg18; + u32 mp0_cluster_cfg19; + u32 mp0_cluster_cfg20; + u32 mp0_cluster_cfg21; + u32 mp0_cluster_cfg22; + u32 mp0_cluster_cfg23; + u32 mp0_mem_dreq_cfg; + u32 mp0_victim_rd_mask; + u32 mp0_minidcc_enable; + u32 mp0_mem_lv_mode; + u8 reserved134[688]; + u32 cpu_type0_spmc0_cfg; + u8 reserved135[28]; + u32 cpu_type0_ram_delsel0_cfg; + u32 cpu_type0_ram_delsel1_cfg; + u32 cpu_type0_ram_delsel2_cfg; + u32 cpu_type0_ram_delsel3_cfg; + u8 reserved136[208]; + u32 cpu_type1_spmc0_cfg; + u8 reserved137[12]; + u32 cpu_type1_mpmmen; + u32 cpu_ppmctl; + u32 cpu_typex_most_on_mode; + u8 reserved138[4]; + u32 cpu_type1_ram_delsel0_cfg; + u32 cpu_type1_ram_delsel1_cfg; + u32 cpu_type1_ram_delsel2_cfg; + u32 cpu_type1_ram_delsel3_cfg; + u8 reserved139[16]; + u32 cpu_type1_drss_cfg0; + u32 cpu_type1_drss_cfg1; + u8 reserved140[216]; + u32 cpu_type2_ram_delsel0_cfg; + u32 cpu_type2_ram_delsel1_cfg; + u32 cpu_type2_ram_delsel2_cfg; + u32 cpu_type2_ram_delsel3_cfg; + u8 reserved141[976]; + u32 mcusys_pwr_con; + u32 mp0_cputop_pwr_con; + u32 mp0_cpu0_pwr_con; + u32 mp0_cpu1_pwr_con; + u32 mp0_cpu2_pwr_con; + u32 mp0_cpu3_pwr_con; + u32 mp0_cpu4_pwr_con; + u32 mp0_cpu5_pwr_con; + u32 mp0_cpu6_pwr_con; + u32 mp0_cpu7_pwr_con; + u8 reserved142[984]; + u32 sec_pol_ctl_en0; + u32 sec_pol_ctl_en1; + u32 sec_pol_ctl_en2; + u32 sec_pol_ctl_en3; + u32 sec_pol_ctl_en4; + u32 sec_pol_ctl_en5; + u32 sec_pol_ctl_en6; + u32 sec_pol_ctl_en7; + u32 sec_pol_ctl_en8; + u32 sec_pol_ctl_en9; + u32 sec_pol_ctl_en10; + u32 sec_pol_ctl_en11; + u32 sec_pol_ctl_en12; + u32 sec_pol_ctl_en13; + u32 sec_pol_ctl_en14; + u32 sec_pol_ctl_en15; + u32 sec_pol_ctl_en16; + u32 sec_pol_ctl_en17; + u32 sec_pol_ctl_en18; + u32 sec_pol_ctl_en19; + u32 sec_pol_ctl_en20; + u32 sec_pol_ctl_en21; + u32 sec_pol_ctl_en22; + u32 sec_pol_ctl_en23; + u32 sec_pol_ctl_en24; + u32 sec_pol_ctl_en25; + u32 sec_pol_ctl_en26; + u32 sec_pol_ctl_en27; + u32 sec_pol_ctl_en28; + u32 sec_pol_ctl_en29; + u32 sec_pol_ctl_en30; + u32 sec_pol_ctl_en31; + u32 int_pol_ctl0; + u32 int_pol_ctl1; + u32 int_pol_ctl2; + u32 int_pol_ctl3; + u32 int_pol_ctl4; + u32 int_pol_ctl5; + u32 int_pol_ctl6; + u32 int_pol_ctl7; + u32 int_pol_ctl8; + u32 int_pol_ctl9; + u32 int_pol_ctl10; + u32 int_pol_ctl11; + u32 int_pol_ctl12; + u32 int_pol_ctl13; + u32 int_pol_ctl14; + u32 int_pol_ctl15; + u32 int_pol_ctl16; + u32 int_pol_ctl17; + u32 int_pol_ctl18; + u32 int_pol_ctl19; + u32 int_pol_ctl20; + u32 int_pol_ctl21; + u32 int_pol_ctl22; + u32 int_pol_ctl23; + u32 int_pol_ctl24; + u32 int_pol_ctl25; + u32 int_pol_ctl26; + u32 int_pol_ctl27; + u32 int_pol_ctl28; + u32 int_pol_ctl29; + u32 int_pol_ctl30; + u32 int_pol_ctl31; + u32 int_msk_ctl0; + u32 int_msk_ctl1; + u32 int_msk_ctl2; + u32 int_msk_ctl3; + u32 int_msk_ctl4; + u32 int_msk_ctl5; + u32 int_msk_ctl6; + u32 int_msk_ctl7; + u32 int_msk_ctl8; + u32 int_msk_ctl9; + u32 int_msk_ctl10; + u32 int_msk_ctl11; + u32 int_msk_ctl12; + u32 int_msk_ctl13; + u32 int_msk_ctl14; + u32 int_msk_ctl15; + u32 int_msk_ctl16; + u32 int_msk_ctl17; + u32 int_msk_ctl18; + u32 int_msk_ctl19; + u32 int_msk_ctl20; + u32 int_msk_ctl21; + u32 int_msk_ctl22; + u32 int_msk_ctl23; + u32 int_msk_ctl24; + u32 int_msk_ctl25; + u32 int_msk_ctl26; + u32 int_msk_ctl27; + u32 int_msk_ctl28; + u32 int_msk_ctl29; + u32 int_msk_ctl30; + u32 int_msk_ctl31; + u32 int_msk_ctl_all; + u32 int_cfg_indirect_access; + u32 int_cfg_direct_access_en; + u8 reserved143[2228]; + u32 dfd_internal_ctl; + u32 dfd_internal_counter; + u32 dfd_internal_pwr_on; + u32 dfd_internal_chain_legth_0; + u32 dfd_internal_shift_clk_ratio; + u32 dfd_internal_counter_return; + u32 dfd_internal_sram_access; + u32 dfd_finish_wait_time; + u32 dfd_internal_chain_group; + u32 dfd_internal_chain_inv_info_ll; + u32 dfd_internal_chain_inv_info_lh; + u32 dfd_internal_chain_inv_info_hl; + u32 dfd_internal_chain_inv_info_hh; + u32 dfd_internal_test_so_over_64; + u32 dfd_internal_mask_out; + u32 dfd_internal_sw_ns_trigger; + u32 dfd_internal_mcsi; + u32 dfd_internal_mcsi_sel_status; + u32 dfd_v30_ctl; + u32 dfd_v30_base_addr; + u32 dfd_power_ctl; + u32 dfd_reset_on; + u32 dfd_test_si_0; + u32 dfd_test_si_1; + u32 dfd_status_clean; + u32 dfd_status_return; + u32 dfd_v35_enable; + u32 dfd_v35_tap_number; + u32 dfd_v35_tap_en; + u32 dfd_v35_ctl; + u32 dfd_v35_tap_seq0; + u32 dfd_v35_tap_seq1; + u32 dfd_v35_seq0_0; + u32 dfd_v35_seq0_1; + u32 dfd_v35_seq1_0; + u32 dfd_v35_seq1_1; + u32 dfd_v35_seq2_0; + u32 dfd_v35_seq2_1; + u8 reserved144[24]; + u32 dfd_soc_clock_stop_mask; + u8 reserved145[8]; + u32 dfd_hw_trigger_mask; + u32 dfd_v50_enable; + u32 dfd_v50_self_trigger_iteration; + u32 dfd_v50_start_trigger; + u32 dfd_v50_cpuck_halt; + u32 dfd_v50_26m_resume; + u32 dfd_v50_26m_halt_release; + u32 dfd_v50_system_halt_time; + u32 dfd_v50_group_0_1_diff; + u32 dfd_v50_group_0_2_diff; + u32 dfd_v50_group_0_3_diff; + u32 dfd_v50_group_0_4_diff; + u32 dfd_v50_group_0_5_diff; + u32 dfd_v50_group_0_6_diff; + u32 dfd_v50_group_0_7_diff; + u32 dfd_v50_group_0_8_diff; + u32 dfd_v50_group_0_9_diff; + u32 dfd_v50_group_0_10_diff; + u32 dfd_v50_group_0_11_diff; + u32 dfd_v50_group_0_12_diff; + u32 dfd_v50_group_0_13_diff; + u32 dfd_v50_group_0_14_diff; + u32 dfd_v50_group_0_15_diff; + u32 dfd_v50_group_0_16_diff; + u32 dfd_v50_group_0_17_diff; + u32 dfd_v50_group_0_18_diff; + u32 dfd_v50_group_0_19_diff; + u32 dfd_v50_group_0_20_diff; + u32 dfd_v50_group_0_21_diff; + u32 dfd_v50_group_0_22_diff; + u32 dfd_v50_group_0_23_diff; + u32 dfd_v50_group_0_24_diff; + u32 dfd_v50_group_0_25_diff; + u32 dfd_v50_group_0_26_diff; + u32 dfd_v50_group_0_27_diff; + u32 dfd_v50_group_0_28_diff; + u32 dfd_v50_group_0_29_diff; + u32 dfd_v50_group_0_30_diff; + u32 dfd_v50_group_0_31_diff; + u32 dfd_v50_chain_group_3_0_info; + u32 dfd_v50_chain_group_7_4_info; + u32 dfd_v50_chain_group_11_8_info; + u32 dfd_v50_chain_group_15_12_info; + u32 dfd_v50_chain_group_19_16_info; + u32 dfd_v50_chain_group_23_20_info; + u32 dfd_v50_chain_group_27_24_info; + u32 dfd_v50_chain_group_31_28_info; + u32 dfd_v50_chain_group_35_32_info; + u32 dfd_v50_chain_group_39_36_info; + u32 dfd_v50_chain_group_43_40_info; + u32 dfd_v50_chain_group_47_44_info; + u32 dfd_v50_chain_group_51_48_info; + u32 dfd_v50_chain_group_55_52_info; + u32 dfd_v50_chain_group_59_56_info; + u32 dfd_v50_chain_group_63_60_info; + u32 dfd_v50_chain_group_67_64_info; + u32 dfd_v50_chain_group_71_68_info; + u32 dfd_v50_chain_group_75_72_info; + u32 dfd_v50_chain_group_79_76_info; + u32 dfd_v50_chain_group_83_80_info; + u32 dfd_v50_chain_group_87_84_info; + u32 dfd_v50_chain_group_91_88_info; + u32 dfd_v50_chain_group_95_92_info; + u32 dfd_v50_chain_group_99_96_info; + u32 dfd_v50_chain_group_103_100_info; + u32 dfd_v50_chain_group_107_104_info; + u32 dfd_v50_chain_group_111_108_info; + u32 dfd_v50_chain_group_115_112_info; + u32 dfd_v50_chain_group_119_116_info; + u32 dfd_v50_chain_group_123_120_info; + u32 dfd_v50_chain_group_127_124_info; + u32 dfd_test_si_2; + u32 dfd_test_si_3; + u32 dfd_test_so; + u32 dfd_bus_halt_time; + u32 dfd_read_addr; + u32 dfd_v50_clk_stop_time; + u32 dfd_v50_group_0_32_diff; + u32 dfd_v50_group_0_33_diff; + u32 dfd_v50_group_0_34_diff; + u32 dfd_v50_group_0_35_diff; + u32 dfd_v50_group_0_36_diff; + u32 dfd_v50_group_0_37_diff; + u32 dfd_v50_group_0_38_diff; + u32 dfd_v50_group_0_39_diff; + u32 dfd_v50_group_0_40_diff; + u32 dfd_v50_group_0_41_diff; + u32 dfd_v50_group_0_42_diff; + u32 dfd_v50_group_0_43_diff; + u32 dfd_v50_group_0_44_diff; + u32 dfd_v50_group_0_45_diff; + u32 dfd_v50_group_0_46_diff; + u32 dfd_v50_group_0_47_diff; + u32 dfd_v50_group_0_48_diff; + u32 dfd_v50_group_0_49_diff; + u32 dfd_v50_group_0_50_diff; + u32 dfd_v50_group_0_51_diff; + u32 dfd_v50_group_0_52_diff; + u32 dfd_v50_group_0_53_diff; + u32 dfd_v50_group_0_54_diff; + u32 dfd_v50_group_0_55_diff; + u32 dfd_v50_group_0_56_diff; + u32 dfd_v50_group_0_57_diff; + u32 dfd_v50_group_0_58_diff; + u32 dfd_v50_group_0_59_diff; + u32 dfd_v50_group_0_60_diff; + u32 dfd_v50_group_0_61_diff; + u32 dfd_v50_group_0_62_diff; + u32 dfd_v50_group_0_63_diff; + u8 reserved146[80]; + u32 dfd_v50_spare; + u8 reserved147[7372]; + u32 mcusys_reserved_reg4; + u32 mcusys_reserved_reg4_rd; + u8 reserved148[8]; + u32 mcusys_reserved_reg0; + u32 mcusys_reserved_reg1; + u32 mcusys_reserved_reg2; + u32 mcusys_reserved_reg3; + u32 mcusys_reserved_reg0_rd; + u32 mcusys_reserved_reg1_rd; + u32 mcusys_reserved_reg2_rd; + u32 mcusys_reserved_reg3_rd; +}; + +check_member(mt8188_mcucfg_regs, cpu_plldiv_cfg0, 0x22a0); +check_member(mt8188_mcucfg_regs, cpu_plldiv_cfg1, 0x22a4); +check_member(mt8188_mcucfg_regs, bus_plldiv_cfg, 0x22e0); + +static struct mt8188_mcucfg_regs *const mtk_mcucfg = (void *)MCUCFG_BASE; + +#endif /* SOC_MEDIATEK_MT8188_MCUCFG_H */ diff --git a/src/soc/mediatek/mt8188/include/soc/pll.h b/src/soc/mediatek/mt8188/include/soc/pll.h index 6b6c123d3e..fb884d30ca 100644 --- a/src/soc/mediatek/mt8188/include/soc/pll.h +++ b/src/soc/mediatek/mt8188/include/soc/pll.h @@ -8,16 +8,411 @@ #ifndef SOC_MEDIATEK_MT8188_PLL_H #define SOC_MEDIATEK_MT8188_PLL_H +#include <device/mmio.h> #include <soc/pll_common.h> +#include <types.h> + +struct mtk_topckgen_regs { + u32 reserved1[1]; + u32 clk_cfg_update; + u32 clk_cfg_update1; + u32 clk_cfg_update2; + u32 clk_cfg_update3; + u32 reserved2[3]; + u32 clk_cfg_0; + u32 clk_cfg_0_set; + u32 clk_cfg_0_clr; + u32 clk_cfg_1; + u32 clk_cfg_1_set; + u32 clk_cfg_1_clr; + u32 clk_cfg_2; + u32 clk_cfg_2_set; + u32 clk_cfg_2_clr; + u32 clk_cfg_3; + u32 clk_cfg_3_set; + u32 clk_cfg_3_clr; + u32 clk_cfg_4; + u32 clk_cfg_4_set; + u32 clk_cfg_4_clr; + u32 clk_cfg_5; + u32 clk_cfg_5_set; + u32 clk_cfg_5_clr; + u32 clk_cfg_6; + u32 clk_cfg_6_set; + u32 clk_cfg_6_clr; + u32 clk_cfg_7; + u32 clk_cfg_7_set; + u32 clk_cfg_7_clr; + u32 clk_cfg_8; + u32 clk_cfg_8_set; + u32 clk_cfg_8_clr; + u32 clk_cfg_9; + u32 clk_cfg_9_set; + u32 clk_cfg_9_clr; + u32 clk_cfg_10; + u32 clk_cfg_10_set; + u32 clk_cfg_10_clr; + u32 clk_cfg_11; + u32 clk_cfg_11_set; + u32 clk_cfg_11_clr; + u32 clk_cfg_12; + u32 clk_cfg_12_set; + u32 clk_cfg_12_clr; + u32 clk_cfg_13; + u32 clk_cfg_13_set; + u32 clk_cfg_13_clr; + u32 clk_cfg_14; + u32 clk_cfg_14_set; + u32 clk_cfg_14_clr; + u32 clk_cfg_15; + u32 clk_cfg_15_set; + u32 clk_cfg_15_clr; + u32 clk_cfg_16; + u32 clk_cfg_16_set; + u32 clk_cfg_16_clr; + u32 clk_cfg_17; + u32 clk_cfg_17_set; + u32 clk_cfg_17_clr; + u32 clk_cfg_18; + u32 clk_cfg_18_set; + u32 clk_cfg_18_clr; + u32 clk_cfg_19; + u32 clk_cfg_19_set; + u32 clk_cfg_19_clr; + u32 clk_cfg_20; + u32 clk_cfg_20_set; + u32 clk_cfg_20_clr; + u32 clk_cfg_21; + u32 clk_cfg_21_set; + u32 clk_cfg_21_clr; + u32 clk_cfg_22; + u32 clk_cfg_22_set; + u32 clk_cfg_22_clr; + u32 clk_cfg_23; + u32 clk_cfg_23_set; + u32 clk_cfg_23_clr; + u32 clk_cfg_24; + u32 clk_cfg_24_set; + u32 clk_cfg_24_clr; + u32 clk_cfg_25; + u32 clk_cfg_25_set; + u32 clk_cfg_25_clr; + u32 clk_cfg_26; + u32 clk_cfg_26_set; + u32 clk_cfg_26_clr; + u32 clk_cfg_27; + u32 clk_cfg_27_set; + u32 clk_cfg_27_clr; + u32 clk_cfg_28; + u32 clk_cfg_28_set; + u32 clk_cfg_28_clr; + u32 clk_cfg_29; + u32 clk_cfg_29_set; + u32 clk_cfg_29_clr; + u32 clk_cfg_30; + u32 clk_cfg_30_set; + u32 clk_cfg_30_clr; + u32 clk_cfg_31; + u32 clk_cfg_31_set; + u32 clk_cfg_31_clr; + u32 clk_cfg_32; + u32 clk_cfg_32_set; + u32 clk_cfg_32_clr; + u32 clk_cfg_33; + u32 clk_cfg_33_set; + u32 clk_cfg_33_clr; + u32 clk_cfg_34; + u32 clk_cfg_34_set; + u32 clk_cfg_34_clr; + u32 clk_cfg_35; + u32 clk_cfg_35_set; + u32 clk_cfg_35_clr; + u32 clk_cfg_36; + u32 clk_cfg_36_set; + u32 clk_cfg_36_clr; + u32 clk_cfg_37; + u32 clk_cfg_37_set; + u32 clk_cfg_37_clr; + u32 reserved3[7]; + u32 clk_extck_reg; + u32 reserved4[1]; + u32 clk_dbg_cfg; + u32 reserved5[2]; + u32 clk26cali_0; + u32 clk26cali_1; + u32 reserved6[3]; + u32 clk_misc_cfg_0; + u32 reserved7[2]; + u32 clk_misc_cfg_1; + u32 reserved8[2]; + u32 clk_misc_cfg_2; + u32 reserved9[2]; + u32 clk_misc_cfg_3; + u32 reserved10[2]; + u32 clk_misc_cfg_6; + u32 reserved11[1]; + u32 clk_scp_cfg_0; +}; +check_member(mtk_topckgen_regs, clk_cfg_update1, 0x0008); +check_member(mtk_topckgen_regs, clk_cfg_0, 0x0020); +check_member(mtk_topckgen_regs, clk_cfg_10_set, 0x009c); +check_member(mtk_topckgen_regs, clk_cfg_10_clr, 0x00a0); +check_member(mtk_topckgen_regs, clk_cfg_11_clr, 0x00ac); +check_member(mtk_topckgen_regs, clk_extck_reg, 0x0204); +check_member(mtk_topckgen_regs, clk26cali_0, 0x0218); +check_member(mtk_topckgen_regs, clk_misc_cfg_0, 0x022c); +check_member(mtk_topckgen_regs, clk_misc_cfg_1, 0x0238); +check_member(mtk_topckgen_regs, clk_misc_cfg_2, 0x0244); +check_member(mtk_topckgen_regs, clk_misc_cfg_3, 0x0250); +check_member(mtk_topckgen_regs, clk_misc_cfg_6, 0x025c); +check_member(mtk_topckgen_regs, clk_scp_cfg_0, 0x264); + +struct mtk_apmixed_regs { + u32 ap_pll_con0; + u32 ap_pll_con1; + u32 ap_pll_con2; + u32 ap_pll_con3; + u32 reserved12[9]; + u32 apll1_tuner_con0; + u32 apll2_tuner_con0; + u32 apll3_tuner_con0; + u32 apll4_tuner_con0; + u32 apll5_tuner_con0; + u32 ref_clk_con0; + u32 ulposc_ctrl_sel; + u32 reserved13[109]; + u32 armpll_ll_con0; + u32 armpll_ll_con1; + u32 armpll_ll_con2; + u32 armpll_ll_con3; + u32 armpll_bl_con0; + u32 armpll_bl_con1; + u32 armpll_bl_con2; + u32 armpll_bl_con3; + u32 ccipll_con0; + u32 ccipll_con1; + u32 ccipll_con2; + u32 ccipll_con3; + u32 reserved14[52]; + u32 apll1_con0; + u32 apll1_con1; + u32 apll1_con2; + u32 apll1_con3; + u32 apll1_con4; + u32 apll2_con0; + u32 apll2_con1; + u32 apll2_con2; + u32 apll2_con3; + u32 apll2_con4; + u32 apll3_con0; + u32 apll3_con1; + u32 apll3_con2; + u32 apll3_con3; + u32 apll3_con4; + u32 mfgpll_con0; + u32 mfgpll_con1; + u32 mfgpll_con2; + u32 mfgpll_con3; + u32 reserved15[45]; + u32 apll4_con0; + u32 apll4_con1; + u32 apll4_con2; + u32 apll4_con3; + u32 apll4_con4; + u32 apll5_con0; + u32 apll5_con1; + u32 apll5_con2; + u32 apll5_con3; + u32 apll5_con4; + u32 adsppll_con0; + u32 adsppll_con1; + u32 adsppll_con2; + u32 adsppll_con3; + u32 mpll_con0; + u32 mpll_con1; + u32 mpll_con2; + u32 mpll_con3; + u32 ethpll_con0; + u32 ethpll_con1; + u32 ethpll_con2; + u32 ethpll_con3; + u32 mainpll_con0; + u32 mainpll_con1; + u32 mainpll_con2; + u32 mainpll_con3; + u32 reserved16[38]; + u32 univpll_con0; + u32 univpll_con1; + u32 univpll_con2; + u32 univpll_con3; + u32 msdcpll_con0; + u32 msdcpll_con1; + u32 msdcpll_con2; + u32 msdcpll_con3; + u32 tvdpll1_con0; + u32 tvdpll1_con1; + u32 tvdpll1_con2; + u32 tvdpll1_con3; + u32 tvdpll2_con0; + u32 tvdpll2_con1; + u32 tvdpll2_con2; + u32 tvdpll2_con3; + u32 mmpll_con0; + u32 mmpll_con1; + u32 mmpll_con2; + u32 mmpll_con3; + u32 imgpll_con0; + u32 imgpll_con1; + u32 imgpll_con2; + u32 imgpll_con3; + u32 reserved17[39]; + u32 ulposc1_con0; + u32 ulposc1_con1; + u32 ulposc1_con2; +}; +check_member(mtk_apmixed_regs, ap_pll_con0, 0x0000); +check_member(mtk_apmixed_regs, apll4_tuner_con0, 0x0040); +check_member(mtk_apmixed_regs, ulposc_ctrl_sel, 0x004c); +check_member(mtk_apmixed_regs, armpll_ll_con0, 0x0204); +check_member(mtk_apmixed_regs, armpll_bl_con3, 0x0220); +check_member(mtk_apmixed_regs, ccipll_con3, 0x0230); +check_member(mtk_apmixed_regs, apll1_con3, 0x0310); +check_member(mtk_apmixed_regs, apll2_con2, 0x0320); +check_member(mtk_apmixed_regs, apll3_con1, 0x0330); +check_member(mtk_apmixed_regs, mainpll_con0, 0x045c); +check_member(mtk_apmixed_regs, univpll_con0, 0x0504); +check_member(mtk_apmixed_regs, mfgpll_con0, 0x0340); +check_member(mtk_apmixed_regs, apll4_con3, 0x0410); +check_member(mtk_apmixed_regs, apll5_con2, 0x0420); +check_member(mtk_apmixed_regs, mpll_con1, 0x0440); +check_member(mtk_apmixed_regs, mainpll_con1, 0x0460); +check_member(mtk_apmixed_regs, univpll_con3, 0x0510); +check_member(mtk_apmixed_regs, msdcpll_con3, 0x0520); +check_member(mtk_apmixed_regs, tvdpll2_con3, 0x0540); +check_member(mtk_apmixed_regs, mmpll_con3, 0x0550); +check_member(mtk_apmixed_regs, imgpll_con3, 0x0560); +check_member(mtk_apmixed_regs, ulposc1_con0, 0x0600); +check_member(mtk_apmixed_regs, ulposc1_con1, 0x0604); +check_member(mtk_apmixed_regs, ulposc1_con2, 0x0608); + +struct mt8188_pericfg_ao_regs { + u32 reserved1[4]; + u32 peri_module_sw_cg_0_set; /* 0x0010 */ + u32 peri_module_sw_cg_0_clr; /* 0x0014 */ +}; +check_member(mt8188_pericfg_ao_regs, peri_module_sw_cg_0_set, 0x0010); +check_member(mt8188_pericfg_ao_regs, peri_module_sw_cg_0_clr, 0x0014); +static struct mt8188_pericfg_ao_regs *const mt8188_pericfg_ao = (void *)PERICFG_AO_BASE; + +enum { + PLL_CKSQ_ON_DELAY = 100, + PLL_PWR_ON_DELAY = 30, + PLL_ISO_DELAY = 1, + PLL_EN_DELAY = 20, +}; + +enum { + PCW_INTEGER_BITS = 8, +}; + +enum { + MT8188_PLL_EN = BIT(9), + MT8188_APLL5_EN = BIT(9) | BIT(20), + GLITCH_FREE_EN = BIT(12), + PLL_DIV_EN = BIT(24) | BIT(25) | BIT(26) | BIT(27) | + BIT(28) | BIT(29) | BIT(30) | BIT(31), +}; + +enum { + MCU_DIV_MASK = 0x1f << 17, + MCU_DIV_1 = 0x8 << 17, + + MCU_MUX_MASK = 0x3 << 9, + MCU_MUX_SRC_PLL = 0x1 << 9, + MCU_MUX_SRC_26M = 0x0 << 9, +}; + +/* PLL rate */ +enum { + ARMPLL_LL_HZ = 500 * MHz, + ARMPLL_BL_HZ = 650 * MHz, + CCIPLL_HZ = 520 * MHz, + ETHPLL_HZ = 500 * MHz, + MSDCPLL_HZ = 384 * MHz, + TVDPLL1_HZ = 594 * MHz, + TVDPLL2_HZ = 594 * MHz, + MMPLL_HZ = 2750UL * MHz, + MAINPLL_HZ = 2184UL * MHz, + IMGPLL_HZ = 660 * MHz, + UNIVPLL_HZ = 2496UL * MHz, + ADSPPLL_HZ = 800 * MHz, + APLL1_HZ = 196608 * KHz, + APLL2_HZ = 180633600, + APLL3_HZ = 196608 * KHz, + APLL4_HZ = 196608 * KHz, + APLL5_HZ = 196608 * KHz, + MFGPLL_HZ = 390 * MHz, +}; /* top_div rate */ enum { - CLK26M_HZ = 26 * MHz, + CLK26M_HZ = 26 * MHz, + UNIVPLL_D6_D2_HZ = UNIVPLL_HZ / 6 / 2, }; /* top_mux rate */ enum { + SPI_HZ = UNIVPLL_D6_D2_HZ, UART_HZ = CLK26M_HZ, }; +DEFINE_BITFIELD(CLK_DBG_CFG_ABIST_CK_SEL, 14, 8) +DEFINE_BITFIELD(CLK_DBG_CFG_CKGEN_CK_SEL, 23, 16) +DEFINE_BITFIELD(CLK_DBG_CFG_METER_CK_SEL, 1, 0) +DEFINE_BITFIELD(CLK_DBG_CFG_CKGEN_EN, 24, 24) +DEFINE_BITFIELD(CLK_MISC_CFG_0_METER_DIV, 31, 24) +DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4) +DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16) + +enum { + INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK = (0x1f << 12) | (0x1 << 17) | (0x1 << 18), + INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON = (0x10 << 12) | (0x1 << 17) | (0x0 << 18), + INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK = (0x1 << 0) | + (0x1 << 1) | + (0x1 << 3) | + (0x1 << 4) | + (0x1f << 5) | + (0x1 << 20) | + (0x1 << 23) | + (0x1 << 30), + INFRACFG_AO_INFRA_BUS_DCM_REG0_ON = (0x1 << 0) | + (0x1 << 1) | + (0x0 << 3) | + (0x0 << 4) | + (0x10 << 5) | + (0x1 << 20) | + (0x1 << 23) | + (0x1 << 30), + INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK = (0xf << 0), + INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON = (0x0 << 0), + INFRACFG_AO_PERI_BUS_DCM_REG0_MASK = (0x1 << 0) | + (0x1 << 1) | + (0x1 << 3) | + (0x1 << 4) | + (0x1f << 5) | + (0x1f << 15) | + (0x1 << 20) | + (0x1 << 21), + INFRACFG_AO_PERI_BUS_DCM_REG0_ON = (0x1 << 0) | + (0x1 << 1) | + (0x0 << 3) | + (0x0 << 4) | + (0x1f << 5) | + (0x1f << 15) | + (0x1 << 20) | + (0x1 << 21), + INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK = (0x1 << 29) | (0x1 << 31), + INFRACFG_AO_PERI_MODULE_DCM_REG0_ON = (0x1 << 29) | (0x1 << 31), +}; + #endif /* SOC_MEDIATEK_MT8188_PLL_H */ diff --git a/src/soc/mediatek/mt8188/include/soc/spm.h b/src/soc/mediatek/mt8188/include/soc/spm.h new file mode 100644 index 0000000000..c388afba34 --- /dev/null +++ b/src/soc/mediatek/mt8188/include/soc/spm.h @@ -0,0 +1,958 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8188_SPM_H +#define SOC_MEDIATEK_MT8188_SPM_H + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/mtcmos.h> +#include <types.h> + +/* SPM READ/WRITE CFG */ +#define SPM_PROJECT_CODE 0xb16 +#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) + +/* POWERON_CONFIG_EN (0x10006000+0x000) */ +#define BCLK_CG_EN_LSB BIT(0) + +/* SPM_CLK_CON (0x10006000+0x00C) */ +DEFINE_BIT(REG_SYSCLK1_SRC_MD2_SRCCLKENA, 28) + +/* PCM_CON0 (0x10006000+0x018) */ +#define PCM_CK_EN_LSB BIT(2) +#define PCM_SW_RESET_LSB BIT(15) + +/* PCM_CON1 (0x10006000+0x01C) */ +#define RG_IM_SLAVE_LSB BIT(0) +#define RG_AHBMIF_APBEN_LSB BIT(3) +#define RG_PCM_TIMER_EN_LSB BIT(5) +#define SPM_EVENT_COUNTER_CLR_LSB BIT(6) +#define RG_PCM_WDT_WAKE_LSB BIT(9) +#define REG_SPM_SRAM_ISOINT_B_LSB BIT(11) +#define REG_EVENT_LOCK_EN_LSB BIT(12) +#define REG_MD32_APB_INTERNAL_EN_LSB BIT(14) + +/* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0D0) */ +#define SPM_WAKEUP_EVENT_MASK_BIT0 BIT(0) +#define SPM_WAKEUP_EVENT_MASK_CSYSPWREQ_B BIT(11) + +/* DDR_EN_DBC_CON1 (0x10006000+0x0EC) */ +#define REG_ALL_DDR_EN_DBC_EN_LSB BIT(0) + +/* SPM_DVFS_MISC (0x10006000+0x4AC) */ +DEFINE_BIT(SPM_DVFS_FORCE_ENABLE_LSB, 2) +DEFINE_BIT(SPM_DVFSRC_ENABLE_LSB, 4) + +/* SPM_SW_FLAG_0 (0x10006000+0x600) */ +#define SPM_FLAG_DISABLE_VCORE_DVS BIT(3) +#define SPM_FLAG_DISABLE_VCORE_DFS BIT(4) +#define SPM_FLAG_RUN_COMMON_SCENARIO BIT(10) + +/* SYS_TIMER_CON (0x10006000+0x98C) */ +DEFINE_BIT(SYS_TIMER_START_EN_LSB, 0) + +/* MD32PCM_CFGREG_SW_RSTN (0x10006000+0xA00) */ +DEFINE_BIT(MD32PCM_CFGREG_SW_RSTN_RESET, 0) + +/************************************** + * Config and Parameter + **************************************/ +#define POWER_ON_VAL1_DEF 0x80015860 +#define SPM_WAKEUP_EVENT_MASK_DEF 0xffffffff +#define SPM_BUS_PROTECT_MASK_B_DEF 0xffffffff +#define SPM_BUS_PROTECT2_MASK_B_DEF 0xffffffff +#define MD32PCM_DMA0_CON_VAL 0x0003820e +#define MD32PCM_DMA0_START_VAL 0x00008000 +#define MD32PCM_CFGREG_SW_RSTN_RUN 0x1 +#define SPM_DVFS_LEVEL_DEF 0x00000001 +#define SPM_DVS_DFS_LEVEL_DEF 0x00010001 +#define SPM_RESOURCE_ACK_CON0_DEF 0xffffffff +#define SPM_RESOURCE_ACK_CON1_DEF 0xffffffff +#define SPM_RESOURCE_ACK_CON2_DEF 0xffffffff +#define SPM_RESOURCE_ACK_CON3_DEF 0xffffffff +#define ARMPLL_CLK_SEL_DEF 0x3ff +#define SPM_SYSCLK_SETTLE 0x60fe +#define SPM_INIT_DONE_US 20 +#define PCM_WDT_TIMEOUT (30 * 32768) +#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT) + +/************************************** + * Definition and Declaration + **************************************/ +/* SPM_IRQ_MASK */ +DEFINE_BIT(ISRM_TWAM_BF, 2) +DEFINE_BITFIELD(ISRM_RET_IRQ_AUX_BF, 17, 8) +#define ISRM_TWAM BIT(2) +#define ISRM_RET_IRQ_AUX (0x3ff << 8) +#define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX) +#define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM) + +/* SPM_IRQ_STA */ +#define ISRS_TWAM BIT(2) +#define ISRS_PCM_RETURN BIT(3) +#define ISRC_TWAM ISRS_TWAM +#define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN +#define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM) + +/* PCM_PWR_IO_EN */ +#define PCM_PWRIO_EN_R0 BIT(0) +#define PCM_PWRIO_EN_R7 BIT(7) +#define PCM_RF_SYNC_R0 BIT(16) +#define PCM_RF_SYNC_R6 BIT(22) +#define PCM_RF_SYNC_R7 BIT(23) + +/* SPM_SWINT */ +#define PCM_SW_INT_ALL 0x3ff + +struct pwr_ctrl { + /* for SPM */ + uint32_t pcm_flags; + /* can override pcm_flags */ + uint32_t pcm_flags_cust; + /* set bit of pcm_flags, after pcm_flags_cust */ + uint32_t pcm_flags_cust_set; + /* clr bit of pcm_flags, after pcm_flags_cust */ + uint32_t pcm_flags_cust_clr; + uint32_t pcm_flags1; + /* can override pcm_flags1 */ + uint32_t pcm_flags1_cust; + /* set bit of pcm_flags1, after pcm_flags1_cust */ + uint32_t pcm_flags1_cust_set; + /* clr bit of pcm_flags1, after pcm_flags1_cust */ + uint32_t pcm_flags1_cust_clr; + /* @ 1T 32K */ + uint32_t timer_val; + /* @ 1T 32K, can override timer_val */ + uint32_t timer_val_cust; + /* stress for dpidle */ + uint32_t timer_val_ramp_en; + /* stress for suspend */ + uint32_t timer_val_ramp_en_sec; + uint32_t wake_src; + /* can override wake_src */ + uint32_t wake_src_cust; + /* disable wdt in suspend */ + uint8_t wdt_disable; + + /* SPM_AP_STANDBY_CON */ + /* [0] */ + uint8_t reg_wfi_op; + /* [1] */ + uint8_t reg_wfi_type; + /* [2] */ + uint8_t reg_mp0_cputop_idle_mask; + /* [3] */ + uint8_t reg_mp1_cputop_idle_mask; + /* [4] */ + uint8_t reg_mcusys_idle_mask; + /* [25] */ + uint8_t reg_md_apsrc_1_sel; + /* [26] */ + uint8_t reg_md_apsrc_0_sel; + /* [29] */ + uint8_t reg_conn_apsrc_sel; + + /* SPM_SRC_REQ */ + /* [0] */ + uint8_t reg_spm_apsrc_req; + /* [1] */ + uint8_t reg_spm_f26m_req; + /* [3] */ + uint8_t reg_spm_infra_req; + /* [4] */ + uint8_t reg_spm_vrf18_req; + /* [7] */ + uint8_t reg_spm_ddr_en_req; + /* [8] */ + uint8_t reg_spm_dvfs_req; + /* [9] */ + uint8_t reg_spm_sw_mailbox_req; + /* [10] */ + uint8_t reg_spm_sspm_mailbox_req; + /* [11] */ + uint8_t reg_spm_adsp_mailbox_req; + /* [12] */ + uint8_t reg_spm_scp_mailbox_req; + + /* SPM_SRC_MASK */ + /* [0] */ + uint8_t reg_sspm_srcclkena_0_mask_b; + /* [1] */ + uint8_t reg_sspm_infra_req_0_mask_b; + /* [2] */ + uint8_t reg_sspm_apsrc_req_0_mask_b; + /* [3] */ + uint8_t reg_sspm_vrf18_req_0_mask_b; + /* [4] */ + uint8_t reg_sspm_ddr_en_0_mask_b; + /* [5] */ + uint8_t reg_scp_srcclkena_mask_b; + /* [6] */ + uint8_t reg_scp_infra_req_mask_b; + /* [7] */ + uint8_t reg_scp_apsrc_req_mask_b; + /* [8] */ + uint8_t reg_scp_vrf18_req_mask_b; + /* [9] */ + uint8_t reg_scp_ddr_en_mask_b; + /* [10] */ + uint8_t reg_audio_dsp_srcclkena_mask_b; + /* [11] */ + uint8_t reg_audio_dsp_infra_req_mask_b; + /* [12] */ + uint8_t reg_audio_dsp_apsrc_req_mask_b; + /* [13] */ + uint8_t reg_audio_dsp_vrf18_req_mask_b; + /* [14] */ + uint8_t reg_audio_dsp_ddr_en_mask_b; + /* [15] */ + uint8_t reg_apu_srcclkena_mask_b; + /* [16] */ + uint8_t reg_apu_infra_req_mask_b; + /* [17] */ + uint8_t reg_apu_apsrc_req_mask_b; + /* [18] */ + uint8_t reg_apu_vrf18_req_mask_b; + /* [19] */ + uint8_t reg_apu_ddr_en_mask_b; + /* [20] */ + uint8_t reg_cpueb_srcclkena_mask_b; + /* [21] */ + uint8_t reg_cpueb_infra_req_mask_b; + /* [22] */ + uint8_t reg_cpueb_apsrc_req_mask_b; + /* [23] */ + uint8_t reg_cpueb_vrf18_req_mask_b; + /* [24] */ + uint8_t reg_cpueb_ddr_en_mask_b; + /* [25] */ + uint8_t reg_bak_psri_srcclkena_mask_b; + /* [26] */ + uint8_t reg_bak_psri_infra_req_mask_b; + /* [27] */ + uint8_t reg_bak_psri_apsrc_req_mask_b; + /* [28] */ + uint8_t reg_bak_psri_vrf18_req_mask_b; + /* [29] */ + uint8_t reg_bak_psri_ddr_en_mask_b; + + /* SPM_SRC2_MASK */ + /* [0] */ + uint8_t reg_msdc0_srcclkena_mask_b; + /* [1] */ + uint8_t reg_msdc0_infra_req_mask_b; + /* [2] */ + uint8_t reg_msdc0_apsrc_req_mask_b; + /* [3] */ + uint8_t reg_msdc0_vrf18_req_mask_b; + /* [4] */ + uint8_t reg_msdc0_ddr_en_mask_b; + /* [5] */ + uint8_t reg_msdc1_srcclkena_mask_b; + /* [6] */ + uint8_t reg_msdc1_infra_req_mask_b; + /* [7] */ + uint8_t reg_msdc1_apsrc_req_mask_b; + /* [8] */ + uint8_t reg_msdc1_vrf18_req_mask_b; + /* [9] */ + uint8_t reg_msdc1_ddr_en_mask_b; + /* [10] */ + uint8_t reg_msdc2_srcclkena_mask_b; + /* [11] */ + uint8_t reg_msdc2_infra_req_mask_b; + /* [12] */ + uint8_t reg_msdc2_apsrc_req_mask_b; + /* [13] */ + uint8_t reg_msdc2_vrf18_req_mask_b; + /* [14] */ + uint8_t reg_msdc2_ddr_en_mask_b; + /* [15] */ + uint8_t reg_ufs_srcclkena_mask_b; + /* [16] */ + uint8_t reg_ufs_infra_req_mask_b; + /* [17] */ + uint8_t reg_ufs_apsrc_req_mask_b; + /* [18] */ + uint8_t reg_ufs_vrf18_req_mask_b; + /* [19] */ + uint8_t reg_ufs_ddr_en_mask_b; + /* [20] */ + uint8_t reg_usb_srcclkena_mask_b; + /* [21] */ + uint8_t reg_usb_infra_req_mask_b; + /* [22] */ + uint8_t reg_usb_apsrc_req_mask_b; + /* [23] */ + uint8_t reg_usb_vrf18_req_mask_b; + /* [24] */ + uint8_t reg_usb_ddr_en_mask_b; + /* [25] */ + uint8_t reg_pextp_p0_srcclkena_mask_b; + /* [26] */ + uint8_t reg_pextp_p0_infra_req_mask_b; + /* [27] */ + uint8_t reg_pextp_p0_apsrc_req_mask_b; + /* [28] */ + uint8_t reg_pextp_p0_vrf18_req_mask_b; + /* [29] */ + uint8_t reg_pextp_p0_ddr_en_mask_b; + + /* SPM_SRC3_MASK */ + /* [0] */ + uint8_t reg_pextp_p1_srcclkena_mask_b; + /* [1] */ + uint8_t reg_pextp_p1_infra_req_mask_b; + /* [2] */ + uint8_t reg_pextp_p1_apsrc_req_mask_b; + /* [3] */ + uint8_t reg_pextp_p1_vrf18_req_mask_b; + /* [4] */ + uint8_t reg_pextp_p1_ddr_en_mask_b; + /* [5] */ + uint8_t reg_gce0_infra_req_mask_b; + /* [6] */ + uint8_t reg_gce0_apsrc_req_mask_b; + /* [7] */ + uint8_t reg_gce0_vrf18_req_mask_b; + /* [8] */ + uint8_t reg_gce0_ddr_en_mask_b; + /* [9] */ + uint8_t reg_gce1_infra_req_mask_b; + /* [10] */ + uint8_t reg_gce1_apsrc_req_mask_b; + /* [11] */ + uint8_t reg_gce1_vrf18_req_mask_b; + /* [12] */ + uint8_t reg_gce1_ddr_en_mask_b; + /* [13] */ + uint8_t reg_spm_srcclkena_reserved_mask_b; + /* [14] */ + uint8_t reg_spm_infra_req_reserved_mask_b; + /* [15] */ + uint8_t reg_spm_apsrc_req_reserved_mask_b; + /* [16] */ + uint8_t reg_spm_vrf18_req_reserved_mask_b; + /* [17] */ + uint8_t reg_spm_ddr_en_reserved_mask_b; + /* [18] */ + uint8_t reg_disp0_apsrc_req_mask_b; + /* [19] */ + uint8_t reg_disp0_ddr_en_mask_b; + /* [20] */ + uint8_t reg_disp1_apsrc_req_mask_b; + /* [21] */ + uint8_t reg_disp1_ddr_en_mask_b; + /* [22] */ + uint8_t reg_disp2_apsrc_req_mask_b; + /* [23] */ + uint8_t reg_disp2_ddr_en_mask_b; + /* [24] */ + uint8_t reg_disp3_apsrc_req_mask_b; + /* [25] */ + uint8_t reg_disp3_ddr_en_mask_b; + /* [26] */ + uint8_t reg_infrasys_apsrc_req_mask_b; + /* [27] */ + uint8_t reg_infrasys_ddr_en_mask_b; + /* [28] */ + uint8_t reg_cg_check_srcclkena_mask_b; + /* [29] */ + uint8_t reg_cg_check_apsrc_req_mask_b; + /* [30] */ + uint8_t reg_cg_check_vrf18_req_mask_b; + /* [31] */ + uint8_t reg_cg_check_ddr_en_mask_b; + + /* SPM_SRC4_MASK */ + /* [8:0] */ + uint32_t reg_mcusys_merge_apsrc_req_mask_b; + /* [17:9] */ + uint32_t reg_mcusys_merge_ddr_en_mask_b; + /* [19:18] */ + uint8_t reg_dramc_md32_infra_req_mask_b; + /* [21:20] */ + uint8_t reg_dramc_md32_vrf18_req_mask_b; + /* [23:22] */ + uint8_t reg_dramc_md32_ddr_en_mask_b; + /* [24] */ + uint8_t reg_dvfsrc_event_trigger_mask_b; + + /* SPM_WAKEUP_EVENT_MASK2 */ + /* [3:0] */ + uint8_t reg_sc_sw2spm_wakeup_mask_b; + /* [4] */ + uint8_t reg_sc_adsp2spm_wakeup_mask_b; + /* [8:5] */ + uint8_t reg_sc_sspm2spm_wakeup_mask_b; + /* [9] */ + uint8_t reg_sc_scp2spm_wakeup_mask_b; + /* [10] */ + uint8_t reg_csyspwrup_ack_mask; + /* [11] */ + uint8_t reg_csyspwrup_req_mask; + + /* SPM_WAKEUP_EVENT_MASK */ + /* [31:0] */ + uint32_t reg_wakeup_event_mask; + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + /* [31:0] */ + uint32_t reg_ext_wakeup_event_mask; +}; + +enum { + DISP_PWR_STA_MASK = BIT(20), + DISP_SRAM_PDN_MASK = BIT(8), + DISP_SRAM_ACK_MASK = BIT(12), + AUDIO_PWR_STA_MASK = BIT(21), + AUDIO_SRAM_PDN_MASK = BIT(8), + AUDIO_SRAM_ACK_MASK = BIT(12), +}; + +struct mtk_spm_regs { + u32 poweron_config_en; + u32 spm_power_on_val0; + u32 spm_power_on_val1; + u32 spm_clk_con; + u32 spm_clk_settle; + u32 spm_ap_standby_con; + u32 pcm_con0; + u32 pcm_con1; + u32 spm_power_on_val2; + u32 spm_power_on_val3; + u32 pcm_reg_data_ini; + u32 pcm_pwr_io_en; + u32 pcm_timer_val; + u32 pcm_wdt_val; + u8 reserved0[8]; + u32 spm_sw_rst_con; + u32 spm_sw_rst_con_set; + u32 spm_sw_rst_con_clr; + u8 reserved1[4]; + u32 spm_arbiter_en; + u32 scpsys_clk_con; + u32 spm_sram_rsv_con; + u32 spm_swint; + u32 spm_swint_set; + u32 spm_swint_clr; + u32 spm_scp_mailbox; + u32 scp_spm_mailbox; + u32 spm_scp_irq; + u32 spm_cpu_wakeup_event; + u32 spm_irq_mask; + u8 reserved2[4]; + u32 spm_src_req; + u32 spm_src_mask; + u32 spm_src2_mask; + u8 reserved3[4]; + u32 spm_src3_mask; + u32 spm_src4_mask; + u32 spm_wakeup_event_mask2; + u32 spm_wakeup_event_mask; + u32 spm_wakeup_event_sens; + u32 spm_wakeup_event_clear; + u32 spm_wakeup_event_ext_mask; + u32 scp_clk_con; + u32 pcm_debug_con; + u32 ddren_dbc_con; + u32 spm_resource_ack_con0; + u32 spm_resource_ack_con1; + u32 spm_resource_ack_con2; + u32 spm_resource_ack_con3; + u32 spm_resource_ack_con4; + u32 spm_sram_con; + u8 reserved4[48]; + u32 pcm_reg0_data; + u32 pcm_reg2_data; + u32 pcm_reg6_data; + u32 pcm_reg7_data; + u32 pcm_reg13_data; + u32 src_req_sta_0; + u32 src_req_sta_1; + u8 reserved5[4]; + u32 src_req_sta_2; + u32 src_req_sta_3; + u32 src_req_sta_4; + u8 reserved6[4]; + u32 pcm_timer_out; + u32 pcm_wdt_out; + u32 spm_irq_sta; + u32 md32pcm_wakeup_sta; + u32 md32pcm_event_sta; + u32 spm_wakeup_sta; + u32 spm_wakeup_ext_sta; + u32 spm_wakeup_misc; + u32 mm_dvfs_halt; + u8 reserved7[16]; + u32 subsys_idle_sta; + u32 pcm_sta; + u32 pwr_status; + u32 pwr_status_2nd; + u32 cpu_pwr_status; + u32 cpu_pwr_status_2nd; + u32 spm_vtcxo_event_count_sta; + u32 spm_infra_event_count_sta; + u32 spm_vrf18_event_count_sta; + u32 spm_apsrc_event_count_sta; + u32 spm_ddren_event_count_sta; + u32 md32pcm_sta; + u32 md32pcm_pc; + u32 other_pwr_status; + u32 dvfsrc_event_sta; + u32 bus_protect_rdy; + u32 bus_protect1_rdy; + u32 bus_protect2_rdy; + u32 bus_protect3_rdy; + u32 bus_protect4_rdy; + u32 bus_protect5_rdy; + u32 bus_protect6_rdy; + u32 bus_protect7_rdy; + u32 bus_protect8_rdy; + u32 bus_protect9_rdy; + u8 reserved8[8]; + u32 spm_twam_last_sta0; + u32 spm_twam_last_sta1; + u32 spm_twam_last_sta2; + u32 spm_twam_last_sta3; + u32 spm_twam_curr_sta0; + u32 spm_twam_curr_sta1; + u32 spm_twam_curr_sta2; + u32 spm_twam_curr_sta3; + u32 spm_twam_timer_out; + u32 spm_cg_check_sta; + u32 spm_dvfs_sta; + u32 spm_dvfs_opp_sta; + u32 cpueb_pwr_con; + u32 spm_mcusys_pwr_con; + u32 spm_cputop_pwr_con; + u32 spm_cpu0_pwr_con; + u32 spm_cpu1_pwr_con; + u32 spm_cpu2_pwr_con; + u32 spm_cpu3_pwr_con; + u32 spm_cpu4_pwr_con; + u32 spm_cpu5_pwr_con; + u32 spm_cpu6_pwr_con; + u32 spm_cpu7_pwr_con; + u32 armpll_clk_con; + u32 mcusys_idle_sta; + u32 gic_wakeup_sta; + u32 cpu_spare_con; + u32 cpu_spare_con_set; + u32 cpu_spare_con_clr; + u32 armpll_clk_sel; + u32 ext_int_wakeup_req; + u32 ext_int_wakeup_req_set; + u32 ext_int_wakeup_req_clr; + u8 reserved9[12]; + u32 cpu_irq_mask; + u32 cpu_irq_mask_set; + u32 cpu_irq_mask_clr; + u8 reserved10[20]; + u32 cpu_wfi_en; + u32 cpu_wfi_en_set; + u32 cpu_wfi_en_clr; + u8 reserved11[4]; + u32 sysram_con; + u32 sysrom_con; + u8 reserved12[8]; + u32 root_cputop_addr; + u32 root_core_addr; + u8 reserved13[40]; + u32 spm2sw_mailbox_0; + u32 spm2sw_mailbox_1; + u32 spm2sw_mailbox_2; + u32 spm2sw_mailbox_3; + u32 sw2spm_int; + u32 sw2spm_int_set; + u32 sw2spm_int_clr; + u32 sw2spm_mailbox_0; + u32 sw2spm_mailbox_1; + u32 sw2spm_mailbox_2; + u32 sw2spm_mailbox_3; + u32 sw2spm_cfg; + u32 mfg0_pwr_con; + u32 mfg1_pwr_con; + u32 mfg2_pwr_con; + u32 mfg3_pwr_con; + u32 mfg4_pwr_con; + u32 mfg5_pwr_con; + u32 ifr_pwr_con; + u32 ifr_sub_pwr_con; + u32 peri_pwr_con; + u32 pextp_mac_top_p0_pwr_con; + u32 pextp_phy_top_pwr_con; + u32 aphy_n_pwr_con; + u32 aphy_s_pwr_con; + u8 reserved14[4]; + u32 ether_pwr_con; + u32 dpy0_pwr_con; + u32 dpy1_pwr_con; + u32 dpm0_pwr_con; + u32 dpm1_pwr_con; + u32 audio_pwr_con; + u32 audio_asrc_pwr_con; + u32 adsp_pwr_con; + u32 adsp_infra_pwr_con; + u32 adsp_ao_pwr_con; + u32 vppsys0_pwr_con; + u32 vppsys1_pwr_con; + u32 vdosys0_pwr_con; + u32 vdosys1_pwr_con; + u32 wpesys_pwr_con; + u32 dp_tx_pwr_con; + u32 edp_tx_pwr_con; + u32 hdmi_tx_pwr_con; + u32 vde0_pwr_con; + u32 vde1_pwr_con; + u32 vde2_pwr_con; + u32 ven_pwr_con; + u32 ven_core1_pwr_con; + u32 cam_main_pwr_con; + u32 cam_suba_pwr_con; + u32 cam_subb_pwr_con; + u32 cam_vcore_pwr_con; + u32 img_vcore_pwr_con; + u32 img_main_pwr_con; + u32 img_dip_pwr_con; + u32 img_ipe_pwr_con; + u32 nna0_pwr_con; + u32 nna1_pwr_con; + u8 reserved15[4]; + u32 ipnna_pwr_con; + u32 csi_rx_top_pwr_con; + u8 reserved16[4]; + u32 sspm_sram_con; + u32 scp_sram_con; + u8 reserved17[4]; + u32 devapc_ifr_sram_con; + u32 devapc_subifr_sram_con; + u32 devapc_acp_sram_con; + u32 usb_sram_con; + u32 dummy_sram_con; + u32 ext_buck_iso; + u32 msdc_sram_con; + u32 debugtop_sram_con; + u32 dpmaif_sram_con; + u32 gcpu_sram_con; + u32 spm_mem_ck_sel; + u32 spm_bus_protect_mask_b; + u32 spm_bus_protect1_mask_b; + u32 spm_bus_protect2_mask_b; + u32 spm_bus_protect3_mask_b; + u32 spm_bus_protect4_mask_b; + u32 spm_bus_protect5_mask_b; + u32 spm_bus_protect6_mask_b; + u32 spm_bus_protect7_mask_b; + u32 spm_bus_protect8_mask_b; + u32 spm_bus_protect9_mask_b; + u32 spm_emi_bw_mode; + u8 reserved18[4]; + u32 spm2mm_con; + u32 spm2cpueb_con; + u32 ap_mdsrc_req; + u32 spm2emi_enter_ulpm; + u32 spm_pll_con; + u32 rc_spm_ctrl; + u32 spm_dram_mcu_sw_con_0; + u32 spm_dram_mcu_sw_con_1; + u32 spm_dram_mcu_sw_con_2; + u32 spm_dram_mcu_sw_con_3; + u32 spm_dram_mcu_sw_con_4; + u32 spm_dram_mcu_sta_0; + u32 spm_dram_mcu_sta_1; + u32 spm_dram_mcu_sta_2; + u32 spm_dram_mcu_sw_sel_0; + u32 relay_dvfs_level; + u32 dramc_dpy_clk_sw_con_0; + u32 dramc_dpy_clk_sw_con_1; + u32 dramc_dpy_clk_sw_con_2; + u32 dramc_dpy_clk_sw_con_3; + u32 dramc_dpy_clk_sw_sel_0; + u32 dramc_dpy_clk_sw_sel_1; + u32 dramc_dpy_clk_sw_sel_2; + u32 dramc_dpy_clk_sw_sel_3; + u32 dramc_dpy_clk_spm_con; + u32 spm_dvfs_level; + u32 spm_cirq_con; + u32 spm_dvfs_misc; + u32 rg_module_sw_cg_0_mask_req_0; + u32 rg_module_sw_cg_0_mask_req_1; + u32 rg_module_sw_cg_0_mask_req_2; + u32 rg_module_sw_cg_1_mask_req_0; + u32 rg_module_sw_cg_1_mask_req_1; + u32 rg_module_sw_cg_1_mask_req_2; + u32 rg_module_sw_cg_2_mask_req_0; + u32 rg_module_sw_cg_2_mask_req_1; + u32 rg_module_sw_cg_2_mask_req_2; + u32 rg_module_sw_cg_3_mask_req_0; + u32 rg_module_sw_cg_3_mask_req_1; + u32 rg_module_sw_cg_3_mask_req_2; + u32 pwr_status_mask_req_0; + u32 pwr_status_mask_req_1; + u32 pwr_status_mask_req_2; + u32 spm_cg_check_con; + u32 spm_src_rdy_sta; + u32 spm_dvs_dfs_level; + u32 spm_force_dvfs; + u32 dramc_mcu_sram_con; + u32 dramc_mcu2_sram_con; + u32 dpy_shu_sram_con; + u32 dpy_shu2_sram_con; + u8 reserved19[20]; + u32 spm_dpm_p2p_sta; + u32 spm_dpm_p2p_con; + u8 reserved20[228]; + u32 spm_sw_flag_0; + u32 spm_sw_debug_0; + u32 spm_sw_flag_1; + u32 spm_sw_debug_1; + u32 spm_sw_rsv_0; + u32 spm_sw_rsv_1; + u32 spm_sw_rsv_2; + u32 spm_sw_rsv_3; + u32 spm_sw_rsv_4; + u32 spm_sw_rsv_5; + u32 spm_sw_rsv_6; + u32 spm_sw_rsv_7; + u32 spm_sw_rsv_8; + u32 spm_bk_wake_event; + u32 spm_bk_vtcxo_dur; + u32 spm_bk_wake_misc; + u32 spm_bk_pcm_timer; + u32 ulposc_con; + u8 reserved21[8]; + u32 spm_rsv_con_0; + u32 spm_rsv_con_1; + u32 spm_rsv_sta_0; + u32 spm_rsv_sta_1; + u32 spm_spare_con; + u32 spm_spare_con_set; + u32 spm_spare_con_clr; + u32 spm_cross_wake_m00_req; + u32 spm_cross_wake_m01_req; + u32 spm_cross_wake_m02_req; + u32 spm_cross_wake_m03_req; + u32 scp_vcore_level; + u32 sc_mm_ck_sel_con; + u32 spare_ack_mask; + u8 reserved22[4]; + u32 spm_dv_con_0; + u32 spm_dv_con_1; + u32 spm_dv_sta; + u32 conn_xowcn_debug_en; + u32 spm_sema_m0; + u32 spm_sema_m1; + u32 spm_sema_m2; + u32 spm_sema_m3; + u32 spm_sema_m4; + u32 spm_sema_m5; + u32 spm_sema_m6; + u32 spm_sema_m7; + u32 spm2adsp_mailbox; + u32 adsp2spm_mailbox; + u32 spm_adsp_irq; + u32 spm_md32_irq; + u32 spm2pmcu_mailbox_0; + u32 spm2pmcu_mailbox_1; + u32 spm2pmcu_mailbox_2; + u32 spm2pmcu_mailbox_3; + u32 pmcu2spm_mailbox_0; + u32 pmcu2spm_mailbox_1; + u32 pmcu2spm_mailbox_2; + u32 pmcu2spm_mailbox_3; + u8 reserved23[12]; + u32 spm_ap_sema; + u32 spm_spm_sema; + u32 spm_dvfs_con; + u32 spm_dvfs_con_sta; + u32 spm_pmic_spmi_con; + u8 reserved24[4]; + u32 spm_dvfs_cmd0; + u32 spm_dvfs_cmd1; + u32 spm_dvfs_cmd2; + u32 spm_dvfs_cmd3; + u32 spm_dvfs_cmd4; + u32 spm_dvfs_cmd5; + u32 spm_dvfs_cmd6; + u32 spm_dvfs_cmd7; + u32 spm_dvfs_cmd8; + u32 spm_dvfs_cmd9; + u32 spm_dvfs_cmd10; + u32 spm_dvfs_cmd11; + u32 spm_dvfs_cmd12; + u32 spm_dvfs_cmd13; + u32 spm_dvfs_cmd14; + u32 spm_dvfs_cmd15; + u32 spm_dvfs_cmd16; + u32 spm_dvfs_cmd17; + u32 spm_dvfs_cmd18; + u32 spm_dvfs_cmd19; + u32 spm_dvfs_cmd20; + u32 spm_dvfs_cmd21; + u32 spm_dvfs_cmd22; + u32 spm_dvfs_cmd23; + u32 sys_timer_value_l; + u32 sys_timer_value_h; + u32 sys_timer_start_l; + u32 sys_timer_start_h; + u32 sys_timer_latch_l_00; + u32 sys_timer_latch_h_00; + u32 sys_timer_latch_l_01; + u32 sys_timer_latch_h_01; + u32 sys_timer_latch_l_02; + u32 sys_timer_latch_h_02; + u32 sys_timer_latch_l_03; + u32 sys_timer_latch_h_03; + u32 sys_timer_latch_l_04; + u32 sys_timer_latch_h_04; + u32 sys_timer_latch_l_05; + u32 sys_timer_latch_h_05; + u32 sys_timer_latch_l_06; + u32 sys_timer_latch_h_06; + u32 sys_timer_latch_l_07; + u32 sys_timer_latch_h_07; + u32 sys_timer_latch_l_08; + u32 sys_timer_latch_h_08; + u32 sys_timer_latch_l_09; + u32 sys_timer_latch_h_09; + u32 sys_timer_latch_l_10; + u32 sys_timer_latch_h_10; + u32 sys_timer_latch_l_11; + u32 sys_timer_latch_h_11; + u32 sys_timer_latch_l_12; + u32 sys_timer_latch_h_12; + u32 sys_timer_latch_l_13; + u32 sys_timer_latch_h_13; + u32 sys_timer_latch_l_14; + u32 sys_timer_latch_h_14; + u32 sys_timer_latch_l_15; + u32 sys_timer_latch_h_15; + u32 pcm_wdt_latch_0; + u32 pcm_wdt_latch_1; + u32 pcm_wdt_latch_2; + u32 pcm_wdt_latch_3; + u32 pcm_wdt_latch_4; + u32 pcm_wdt_latch_5; + u32 pcm_wdt_latch_6; + u32 pcm_wdt_latch_7; + u32 pcm_wdt_latch_8; + u32 pcm_wdt_latch_9; + u32 pcm_wdt_latch_10; + u32 pcm_wdt_latch_11; + u32 pcm_wdt_latch_12; + u32 pcm_wdt_latch_13; + u32 pcm_wdt_latch_14; + u32 pcm_wdt_latch_15; + u32 pcm_wdt_latch_16; + u32 pcm_wdt_latch_17; + u32 pcm_wdt_latch_18; + u32 pcm_wdt_latch_spare_0; + u32 pcm_wdt_latch_spare_1; + u32 pcm_wdt_latch_spare_2; + u8 reserved25[72]; + u32 dramc_gating_err_latch_ch0_0; + u32 dramc_gating_err_latch_ch0_1; + u32 dramc_gating_err_latch_ch0_2; + u32 dramc_gating_err_latch_ch0_3; + u32 dramc_gating_err_latch_ch0_4; + u32 dramc_gating_err_latch_ch0_5; + u8 reserved26[60]; + u32 dramc_gating_err_latch_spare_0; + u8 reserved27[8]; + u32 spm_ack_chk_con_0; + u32 spm_ack_chk_pc_0; + u32 spm_ack_chk_sel_0; + u32 spm_ack_chk_timer_0; + u32 spm_ack_chk_sta_0; + u32 spm_ack_chk_swint_0; + u8 reserved28[8]; + u32 spm_ack_chk_con_1; + u32 spm_ack_chk_pc_1; + u32 spm_ack_chk_sel_1; + u32 spm_ack_chk_timer_1; + u32 spm_ack_chk_sta_1; + u32 spm_ack_chk_swint_1; + u8 reserved29[8]; + u32 spm_ack_chk_con_2; + u32 spm_ack_chk_pc_2; + u32 spm_ack_chk_sel_2; + u32 spm_ack_chk_timer_2; + u32 spm_ack_chk_sta_2; + u32 spm_ack_chk_swint_2; + u8 reserved30[8]; + u32 spm_ack_chk_con_3; + u32 spm_ack_chk_pc_3; + u32 spm_ack_chk_sel_3; + u32 spm_ack_chk_timer_3; + u32 spm_ack_chk_sta_3; + u32 spm_ack_chk_swint_3; + u32 spm_counter_0; + u32 spm_counter_1; + u32 spm_counter_2; + u8 reserved31[8]; + u32 sys_timer_con; + u32 spm_twam_con; + u32 spm_twam_window_len; + u32 spm_twam_idle_sel; + u32 spm_twam_event_clear; + u8 reserved32[1376]; + u32 pmsr_last_dat; + u32 pmsr_last_cnt; + u32 pmsr_last_ack; + u8 reserved33[4]; + u32 spm_pmsr_sel_con0; + u32 spm_pmsr_sel_con1; + u32 spm_pmsr_sel_con2; + u32 spm_pmsr_sel_con3; + u32 spm_pmsr_sel_con4; + u32 spm_pmsr_sel_con5; + u32 spm_pmsr_sel_con6; + u32 spm_pmsr_sel_con7; + u32 spm_pmsr_sel_con8; + u32 spm_pmsr_sel_con9; + u8 reserved34[4]; + u32 spm_pmsr_sel_con10; + u32 spm_pmsr_sel_con11; + u8 reserved35[116]; + u32 spm_pmsr_tiemr_sta0; + u32 spm_pmsr_tiemr_sta1; + u32 spm_pmsr_tiemr_sta2; + u32 spm_pmsr_general_con0; + u32 spm_pmsr_general_con1; + u32 spm_pmsr_general_con2; + u32 spm_pmsr_general_con3; + u32 spm_pmsr_general_con4; + u32 spm_pmsr_general_con5; + u32 spm_pmsr_sw_reset; + u32 spm_pmsr_mon_con0; + u32 spm_pmsr_mon_con1; + u32 spm_pmsr_mon_con2; + u32 spm_pmsr_len_con0; + u32 spm_pmsr_len_con1; + u32 spm_pmsr_len_con2; +}; + +check_member(mtk_spm_regs, pwr_status, 0x016c); +check_member(mtk_spm_regs, audio_pwr_con, 0x034c); +check_member(mtk_spm_regs, adsp_pwr_con, 0x0354); +check_member(mtk_spm_regs, ap_mdsrc_req, 0x043c); +check_member(mtk_spm_regs, ulposc_con, 0x644); + +static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; + +struct pcm_desc { + u32 pmem_words; + u32 total_words; + u32 pmem_start; + u32 dmem_start; +}; + +struct dyna_load_pcm { + u8 *buf; /* binary array */ + struct pcm_desc desc; +}; + +int spm_init(void); + +#endif /* SOC_MEDIATEK_MT8188_SPM_H */ diff --git a/src/soc/mediatek/mt8188/pll.c b/src/soc/mediatek/mt8188/pll.c new file mode 100644 index 0000000000..71fefbe8e0 --- /dev/null +++ b/src/soc/mediatek/mt8188/pll.c @@ -0,0 +1,720 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/mmio.h> +#include <delay.h> +#include <stddef.h> +#include <timer.h> + +#include <soc/addressmap.h> +#include <soc/infracfg.h> +#include <soc/mcucfg.h> +#include <soc/pll.h> +#include <soc/spm.h> +#include <soc/wdt.h> + +enum mux_id { + TOP_AXI_SEL, + TOP_SPM_SEL, + TOP_SCP_SEL, + TOP_BUS_AXIMEM_SEL, + TOP_VPP_SEL, + TOP_ETHDR_SEL, + TOP_IPE_SEL, + TOP_CAM_SEL, + TOP_CCU_SEL, + TOP_CCU_AHB_SEL, + TOP_IMG_SEL, + TOP_CAMTM_SEL, + TOP_DSP_SEL, + TOP_DSP1_SEL, + TOP_DSP2_SEL, + TOP_DSP3_SEL, + TOP_DSP4_SEL, + TOP_DSP5_SEL, + TOP_DSP6_SEL, + TOP_DSP7_SEL, + TOP_MFG_CORE_TMP_SEL, + TOP_CAMTG_SEL, + TOP_CAMTG2_SEL, + TOP_CAMTG3_SEL, + TOP_UART_SEL, + TOP_SPI_SEL, + TOP_MSDC50_0_HSEL, + TOP_MSDC50_0_SEL, + TOP_MSDC30_1_SEL, + TOP_MSDC30_2_SEL, + TOP_INTDIR_SEL, + TOP_AUD_INTBUS_SEL, + TOP_AUDIO_H_SEL, + TOP_PWRAP_ULPOSC_SEL, + TOP_ATB_SEL, + TOP_SSPM_SEL, + TOP_DP_SEL, + TOP_EDP_SEL, + TOP_DPI_SEL, + TOP_DISP_PWM0_SEL, + TOP_DISP_PWM1_SEL, + TOP_USB_TOP_SEL, + TOP_SSUSB_XHCI_SEL, + TOP_USB_TOP_2P_SEL, + TOP_SSUSB_XHCI_2P_SEL, + TOP_USB_TOP_3P_SEL, + TOP_SSUSB_XHCI_3P_SEL, + TOP_I2C_SEL, + TOP_SENINF_SEL, + TOP_SENINF1_SEL, + TOP_GCPU_SEL, + TOP_VENC_SEL, + TOP_VDEC_SEL, + TOP_PWM_SEL, + TOP_MCUPM_SEL, + TOP_SPMI_P_MST_SEL, + TOP_SPMI_M_MST_SEL, + TOP_DVFSRC_SEL, + TOP_TL_SEL, + TOP_AES_MSDCFDE_SEL, + TOP_DSI_OCC_SEL, + TOP_WPE_VPP_SEL, + TOP_HDCP_SEL, + TOP_HDCP_24M_SEL, + TOP_HDMI_APB_SEL, + TOP_SNPS_ETH_250M_SEL, + TOP_SNPS_ETH_62P4M_PTP_SEL, + TOP_SNPS_ETH_50M_RMII_SEL, + TOP_ADSP_SEL, + TOP_AUDIO_LOCAL_BUS_SEL, + TOP_ASM_H_SEL, + TOP_ASM_L_SEL, + TOP_APLL1_SEL, + TOP_APLL2_SEL, + TOP_APLL3_SEL, + TOP_APLL4_SEL, + TOP_APLL5_SEL, + TOP_I2SO1_SEL, + TOP_I2SO2_SEL, + TOP_I2SI1_SEL, + TOP_I2SI2_SEL, + TOP_DPTX_SEL, + TOP_AUD_IEC_SEL, + TOP_A1SYS_HP_SEL, + TOP_A2SYS_SEL, + TOP_A3SYS_SEL, + TOP_A4SYS_SEL, + TOP_ECC_SEL, + TOP_SPINOR_SEL, + TOP_ULPOSC_SEL, + TOP_SRCK_SEL, + TOP_MFG_CK_FAST_REF_SEL, + TOP_NR_MUX +}; + +#define MUX(_id, _reg, _mux_shift, _mux_width) \ + [_id] = { \ + .reg = &mtk_topckgen->_reg, \ + .mux_shift = _mux_shift, \ + .mux_width = _mux_width, \ + } + +#define MUX_UPD(_id, _reg, _mux_shift, _mux_width, _upd_reg, _upd_shift)\ + [_id] = { \ + .reg = &mtk_topckgen->_reg, \ + .set_reg = &mtk_topckgen->_reg##_set, \ + .clr_reg = &mtk_topckgen->_reg##_clr, \ + .mux_shift = _mux_shift, \ + .mux_width = _mux_width, \ + .upd_reg = &mtk_topckgen->_upd_reg, \ + .upd_shift = _upd_shift, \ + } + +static const struct mux muxes[] = { + /* CLK_CFG_0 */ + MUX_UPD(TOP_AXI_SEL, clk_cfg_0, 0, 3, clk_cfg_update, 0), + MUX_UPD(TOP_SPM_SEL, clk_cfg_0, 8, 2, clk_cfg_update, 1), + MUX_UPD(TOP_SCP_SEL, clk_cfg_0, 16, 3, clk_cfg_update, 2), + MUX_UPD(TOP_BUS_AXIMEM_SEL, clk_cfg_0, 24, 3, clk_cfg_update, 3), + /* CLK_CFG_1 */ + MUX_UPD(TOP_VPP_SEL, clk_cfg_1, 0, 4, clk_cfg_update, 4), + MUX_UPD(TOP_ETHDR_SEL, clk_cfg_1, 8, 4, clk_cfg_update, 5), + MUX_UPD(TOP_IPE_SEL, clk_cfg_1, 16, 4, clk_cfg_update, 6), + MUX_UPD(TOP_CAM_SEL, clk_cfg_1, 24, 4, clk_cfg_update, 7), + /* CLK_CFG_2 */ + MUX_UPD(TOP_CCU_SEL, clk_cfg_2, 0, 4, clk_cfg_update, 8), + MUX_UPD(TOP_CCU_AHB_SEL, clk_cfg_2, 8, 4, clk_cfg_update, 9), + MUX_UPD(TOP_IMG_SEL, clk_cfg_2, 16, 2, clk_cfg_update, 10), + MUX_UPD(TOP_CAMTM_SEL, clk_cfg_2, 24, 3, clk_cfg_update, 11), + /* CLK_CFG_3 */ + MUX_UPD(TOP_DSP_SEL, clk_cfg_3, 0, 3, clk_cfg_update, 12), + MUX_UPD(TOP_DSP1_SEL, clk_cfg_3, 8, 3, clk_cfg_update, 13), + MUX_UPD(TOP_DSP2_SEL, clk_cfg_3, 16, 3, clk_cfg_update, 14), + MUX_UPD(TOP_DSP3_SEL, clk_cfg_3, 24, 3, clk_cfg_update, 15), + /* CLK_CFG_4 */ + MUX_UPD(TOP_DSP4_SEL, clk_cfg_4, 0, 3, clk_cfg_update, 16), + MUX_UPD(TOP_DSP5_SEL, clk_cfg_4, 8, 3, clk_cfg_update, 17), + MUX_UPD(TOP_DSP6_SEL, clk_cfg_4, 16, 3, clk_cfg_update, 18), + MUX_UPD(TOP_DSP7_SEL, clk_cfg_4, 24, 3, clk_cfg_update, 19), + /* CLK_CFG_5 */ + MUX_UPD(TOP_MFG_CORE_TMP_SEL, clk_cfg_5, 0, 2, clk_cfg_update, 20), + MUX_UPD(TOP_CAMTG_SEL, clk_cfg_5, 8, 3, clk_cfg_update, 21), + MUX_UPD(TOP_CAMTG2_SEL, clk_cfg_5, 16, 3, clk_cfg_update, 22), + MUX_UPD(TOP_CAMTG3_SEL, clk_cfg_5, 24, 3, clk_cfg_update, 23), + /* CLK_CFG_6 */ + MUX_UPD(TOP_UART_SEL, clk_cfg_6, 0, 3, clk_cfg_update, 24), + MUX_UPD(TOP_SPI_SEL, clk_cfg_6, 8, 3, clk_cfg_update, 25), + MUX_UPD(TOP_MSDC50_0_HSEL, clk_cfg_6, 16, 1, clk_cfg_update, 26), + MUX_UPD(TOP_MSDC50_0_SEL, clk_cfg_6, 24, 3, clk_cfg_update, 27), + /* CLK_CFG_7 */ + MUX_UPD(TOP_MSDC30_1_SEL, clk_cfg_7, 0, 3, clk_cfg_update, 28), + MUX_UPD(TOP_MSDC30_2_SEL, clk_cfg_7, 8, 2, clk_cfg_update, 29), + MUX_UPD(TOP_INTDIR_SEL, clk_cfg_7, 16, 3, clk_cfg_update, 30), + MUX_UPD(TOP_AUD_INTBUS_SEL, clk_cfg_7, 24, 3, clk_cfg_update, 31), + /* CLK_CFG_8 */ + MUX_UPD(TOP_AUDIO_H_SEL, clk_cfg_8, 0, 3, clk_cfg_update1, 0), + MUX_UPD(TOP_PWRAP_ULPOSC_SEL, clk_cfg_8, 8, 2, clk_cfg_update1, 1), + MUX_UPD(TOP_ATB_SEL, clk_cfg_8, 16, 2, clk_cfg_update1, 2), + MUX_UPD(TOP_SSPM_SEL, clk_cfg_8, 24, 2, clk_cfg_update1, 3), + /* CLK_CFG_9 */ + MUX_UPD(TOP_DP_SEL, clk_cfg_9, 0, 3, clk_cfg_update1, 4), + MUX_UPD(TOP_EDP_SEL, clk_cfg_9, 8, 2, clk_cfg_update1, 5), + MUX_UPD(TOP_DPI_SEL, clk_cfg_9, 16, 3, clk_cfg_update1, 6), + MUX_UPD(TOP_DISP_PWM0_SEL, clk_cfg_9, 24, 4, clk_cfg_update1, 7), + /* CLK_CFG_10 */ + MUX_UPD(TOP_DISP_PWM1_SEL, clk_cfg_10, 0, 4, clk_cfg_update1, 8), + MUX_UPD(TOP_USB_TOP_SEL, clk_cfg_10, 8, 4, clk_cfg_update1, 9), + MUX_UPD(TOP_SSUSB_XHCI_SEL, clk_cfg_10, 16, 3, clk_cfg_update1, 10), + MUX_UPD(TOP_USB_TOP_2P_SEL, clk_cfg_10, 24, 3, clk_cfg_update1, 11), + /* CLK_CFG_11 */ + MUX_UPD(TOP_SSUSB_XHCI_2P_SEL, clk_cfg_11, 0, 2, clk_cfg_update1, 12), + MUX_UPD(TOP_USB_TOP_3P_SEL, clk_cfg_11, 8, 2, clk_cfg_update1, 13), + MUX_UPD(TOP_SSUSB_XHCI_3P_SEL, clk_cfg_11, 16, 2, clk_cfg_update1, 14), + MUX_UPD(TOP_I2C_SEL, clk_cfg_11, 24, 2, clk_cfg_update1, 15), + /* CLK_CFG_12 */ + MUX_UPD(TOP_SENINF_SEL, clk_cfg_12, 0, 2, clk_cfg_update1, 16), + MUX_UPD(TOP_SENINF1_SEL, clk_cfg_12, 8, 2, clk_cfg_update1, 17), + MUX_UPD(TOP_GCPU_SEL, clk_cfg_12, 16, 2, clk_cfg_update1, 18), + MUX_UPD(TOP_VENC_SEL, clk_cfg_12, 24, 2, clk_cfg_update1, 19), + /* CLK_CFG_13 */ + MUX_UPD(TOP_VDEC_SEL, clk_cfg_13, 0, 2, clk_cfg_update1, 20), + MUX_UPD(TOP_PWM_SEL, clk_cfg_13, 8, 3, clk_cfg_update1, 21), + MUX_UPD(TOP_MCUPM_SEL, clk_cfg_13, 16, 3, clk_cfg_update1, 22), + MUX_UPD(TOP_SPMI_P_MST_SEL, clk_cfg_13, 24, 3, clk_cfg_update1, 23), + /* CLK_CFG_14 */ + MUX_UPD(TOP_SPMI_M_MST_SEL, clk_cfg_14, 0, 3, clk_cfg_update1, 24), + MUX_UPD(TOP_DVFSRC_SEL, clk_cfg_14, 8, 3, clk_cfg_update1, 25), + MUX_UPD(TOP_TL_SEL, clk_cfg_14, 16, 2, clk_cfg_update1, 26), + MUX_UPD(TOP_AES_MSDCFDE_SEL, clk_cfg_14, 24, 3, clk_cfg_update1, 27), + /* CLK_CFG_15 */ + MUX_UPD(TOP_DSI_OCC_SEL, clk_cfg_15, 0, 3, clk_cfg_update1, 28), + MUX_UPD(TOP_WPE_VPP_SEL, clk_cfg_15, 8, 3, clk_cfg_update1, 29), + MUX_UPD(TOP_HDCP_SEL, clk_cfg_15, 16, 1, clk_cfg_update1, 30), + MUX_UPD(TOP_HDCP_24M_SEL, clk_cfg_15, 24, 1, clk_cfg_update1, 31), + /* CLK_CFG_16 */ + MUX_UPD(TOP_HDMI_APB_SEL, clk_cfg_16, 0, 4, clk_cfg_update2, 0), + MUX_UPD(TOP_SNPS_ETH_250M_SEL, clk_cfg_16, 8, 4, clk_cfg_update2, 1), + MUX_UPD(TOP_SNPS_ETH_62P4M_PTP_SEL, clk_cfg_16, 16, 1, clk_cfg_update2, 2), + MUX_UPD(TOP_SNPS_ETH_50M_RMII_SEL, clk_cfg_16, 24, 2, clk_cfg_update2, 3), + /* CLK_CFG_17 */ + MUX_UPD(TOP_ADSP_SEL, clk_cfg_17, 0, 4, clk_cfg_update2, 4), + MUX_UPD(TOP_AUDIO_LOCAL_BUS_SEL, clk_cfg_17, 8, 4, clk_cfg_update2, 5), + MUX_UPD(TOP_ASM_H_SEL, clk_cfg_17, 16, 2, clk_cfg_update2, 6), + MUX_UPD(TOP_ASM_L_SEL, clk_cfg_17, 24, 2, clk_cfg_update2, 7), + /* CLK_CFG_18 */ + MUX_UPD(TOP_APLL1_SEL, clk_cfg_18, 0, 2, clk_cfg_update2, 8), + MUX_UPD(TOP_APLL2_SEL, clk_cfg_18, 8, 3, clk_cfg_update2, 9), + MUX_UPD(TOP_APLL3_SEL, clk_cfg_18, 16, 2, clk_cfg_update2, 10), + MUX_UPD(TOP_APLL4_SEL, clk_cfg_18, 24, 4, clk_cfg_update2, 11), + /* CLK_CFG_19 */ + MUX_UPD(TOP_APLL5_SEL, clk_cfg_19, 0, 2, clk_cfg_update2, 12), + MUX_UPD(TOP_I2SO1_SEL, clk_cfg_19, 8, 2, clk_cfg_update2, 13), + MUX_UPD(TOP_I2SO2_SEL, clk_cfg_19, 16, 2, clk_cfg_update2, 14), + MUX_UPD(TOP_I2SI1_SEL, clk_cfg_19, 24, 2, clk_cfg_update2, 15), + /* CLK_CFG_20 */ + MUX_UPD(TOP_I2SI2_SEL, clk_cfg_20, 0, 1, clk_cfg_update2, 16), + MUX_UPD(TOP_DPTX_SEL, clk_cfg_20, 8, 2, clk_cfg_update2, 17), + MUX_UPD(TOP_AUD_IEC_SEL, clk_cfg_20, 16, 1, clk_cfg_update2, 18), + MUX_UPD(TOP_A1SYS_HP_SEL, clk_cfg_20, 24, 2, clk_cfg_update2, 19), + /* CLK_CFG_21 */ + MUX_UPD(TOP_A2SYS_SEL, clk_cfg_21, 0, 1, clk_cfg_update2, 20), + MUX_UPD(TOP_A3SYS_SEL, clk_cfg_21, 8, 3, clk_cfg_update2, 21), + MUX_UPD(TOP_A4SYS_SEL, clk_cfg_21, 16, 4, clk_cfg_update2, 22), + MUX_UPD(TOP_ECC_SEL, clk_cfg_21, 24, 4, clk_cfg_update2, 23), + /* CLK_CFG_22 */ + MUX_UPD(TOP_SPINOR_SEL, clk_cfg_22, 0, 4, clk_cfg_update2, 24), + MUX_UPD(TOP_ULPOSC_SEL, clk_cfg_22, 8, 2, clk_cfg_update2, 25), + MUX_UPD(TOP_SRCK_SEL, clk_cfg_22, 16, 2, clk_cfg_update2, 26), +}; + +struct mux_sel { + enum mux_id id; + u32 sel; +}; + +static const struct mux_sel mux_sels[] = { + /* CLK_CFG_0 */ + { .id = TOP_AXI_SEL, .sel = 2 }, /* 2: mainpll_d7_d2 */ + { .id = TOP_SPM_SEL, .sel = 2 }, /* 2: mainpll_d7_d4 */ + { .id = TOP_SCP_SEL, .sel = 5 }, /* 5: mainpll_d4_d2 */ + { .id = TOP_BUS_AXIMEM_SEL, .sel = 1 }, /* 1: mainpll_d7_d2 */ + /* CLK_CFG_1 */ + { .id = TOP_VPP_SEL, .sel = 8 }, /* 8: mainpll_d6 */ + { .id = TOP_ETHDR_SEL, .sel = 10 }, /* 10: mmpll_d5_d4 */ + { .id = TOP_IPE_SEL, .sel = 8 }, /* 8: mainpll_d4_d2 */ + { .id = TOP_CAM_SEL, .sel = 8 }, /* 8: mainpll_d4_d2 */ + /* CLK_CFG_2 */ + { .id = TOP_CCU_SEL, .sel = 2 }, /* 2: mainpll_d4_d2 */ + { .id = TOP_CCU_AHB_SEL, .sel = 11 }, /* 11: univpll_d5_d2 */ + { .id = TOP_IMG_SEL, .sel = 2 }, /* 2: univpll_d6_d2 */ + { .id = TOP_CAMTM_SEL, .sel = 7 }, /* 7: univpll_d3 */ + /* CLK_CFG_3 */ + { .id = TOP_DSP_SEL, .sel = 7 }, /* 7: univpll_d3 */ + { .id = TOP_DSP1_SEL, .sel = 7 }, /* 7: univpll_d3 */ + { .id = TOP_DSP2_SEL, .sel = 7 }, /* 7: univpll_d3 */ + { .id = TOP_DSP3_SEL, .sel = 7 }, /* 7: univpll_d3 */ + /* CLK_CFG_4 */ + { .id = TOP_DSP4_SEL, .sel = 7 }, /* 7: univpll_d3 */ + { .id = TOP_DSP5_SEL, .sel = 7 }, /* 7: univpll_d3 */ + { .id = TOP_DSP6_SEL, .sel = 7 }, /* 7: univpll_d3 */ + { .id = TOP_DSP7_SEL, .sel = 7 }, /* 7: mmpll_d4 */ + /* CLK_CFG_5 */ + { .id = TOP_MFG_CORE_TMP_SEL, .sel = 3 }, /* 3: univpll_d7 */ + { .id = TOP_CAMTG_SEL, .sel = 2 }, /* 2: univpll_d6_d8 */ + { .id = TOP_CAMTG2_SEL, .sel = 2 }, /* 2: univpll_d6_d8 */ + { .id = TOP_CAMTG3_SEL, .sel = 2 }, /* 2: univpll_d6_d8 */ + /* CLK_CFG_6 */ + { .id = TOP_UART_SEL, .sel = 0 }, /* 0: clk26m */ + { .id = TOP_SPI_SEL, .sel = 4 }, /* 4: univpll_d6_d2 */ + { .id = TOP_MSDC50_0_HSEL, .sel = 1 }, /* 1: mainpll_d4_d2 */ + { .id = TOP_MSDC50_0_SEL, .sel = 1 }, /* 1: msdcpll_ck */ + /* CLK_CFG_7 */ + { .id = TOP_MSDC30_1_SEL, .sel = 1 }, /* 1: univpll_d6_d2 */ + { .id = TOP_MSDC30_2_SEL, .sel = 1 }, /* 1: univpll_d6_d2 */ + { .id = TOP_INTDIR_SEL, .sel = 3 }, /* 3: univpll_d4 */ + { .id = TOP_AUD_INTBUS_SEL, .sel = 1 }, /* 1: mainpll_d4_d4 */ + /* CLK_CFG_8 */ + { .id = TOP_AUDIO_H_SEL, .sel = 2 }, /* 2: apll1_ck */ + { .id = TOP_PWRAP_ULPOSC_SEL, .sel = 1 }, /* 1: ulposc_d10 */ + { .id = TOP_ATB_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */ + { .id = TOP_SSPM_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */ + /* CLK_CFG_9 */ + { .id = TOP_DP_SEL, .sel = 3 }, /* 3: tvdpll1_d4 */ + { .id = TOP_EDP_SEL, .sel = 4 }, /* 4: tvdpll2_d4 */ + { .id = TOP_DPI_SEL, .sel = 2 }, /* 2: tvdpll1_d2 */ + { .id = TOP_DISP_PWM0_SEL, .sel = 2 }, /* 2: ulposc_d2 */ + /* CLK_CFG_10 */ + { .id = TOP_DISP_PWM1_SEL, .sel = 2 }, /* 2: ulposc_d2 */ + { .id = TOP_USB_TOP_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */ + { .id = TOP_SSUSB_XHCI_SEL, .sel = 1 }, /* 1: univpll_d6_d4 */ + { .id = TOP_USB_TOP_2P_SEL, .sel = 1 }, /* 1: univpll_d6_d4 */ + /* CLK_CFG_11 */ + { .id = TOP_SSUSB_XHCI_2P_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */ + { .id = TOP_USB_TOP_3P_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */ + { .id = TOP_SSUSB_XHCI_3P_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */ + { .id = TOP_I2C_SEL, .sel = 2 }, /* 2: univpll_d5_d4 */ + /* CLK_CFG_12 */ + { .id = TOP_SENINF_SEL, .sel = 3 }, /* 3: mainpll_d4_d2 */ + { .id = TOP_SENINF1_SEL, .sel = 3 }, /* 3: mainpll_d4_d2 */ + { .id = TOP_GCPU_SEL, .sel = 3 }, /* 3: mmpll_d5_d2 */ + { .id = TOP_VENC_SEL, .sel = 14 }, /* 14: univpll_d5_d2 */ + /* CLK_CFG_13 */ + { .id = TOP_VDEC_SEL, .sel = 1 }, /* 1: mainpll_d5_d2 */ + { .id = TOP_PWM_SEL, .sel = 3 }, /* 3: univpll_d6_d4 */ + { .id = TOP_MCUPM_SEL, .sel = 1 }, /* 1: mainpll_d6_d2 */ + { .id = TOP_SPMI_P_MST_SEL, .sel = 7 }, /* 7: mainpll_d7_d8 */ + /* CLK_CFG_14 */ + { .id = TOP_SPMI_M_MST_SEL, .sel = 7 }, /* 7: mainpll_d7_d8 */ + { .id = TOP_DVFSRC_SEL, .sel = 0 }, /* 0: clk26m */ + { .id = TOP_TL_SEL, .sel = 2 }, /* 2: mainpll_d4_d4 */ + { .id = TOP_AES_MSDCFDE_SEL, .sel = 5 }, /* 5: univpll_d6 */ + /* CLK_CFG_15 */ + { .id = TOP_DSI_OCC_SEL, .sel = 1 }, /* 1: univpll_d6_d2 */ + { .id = TOP_WPE_VPP_SEL, .sel = 7 }, /* 7: mainpll_d6 */ + { .id = TOP_HDCP_SEL, .sel = 3 }, /* 3: univpll_d6_d4 */ + { .id = TOP_HDCP_24M_SEL, .sel = 1 }, /* 1: univpll_192m_d4 */ + /* CLK_CFG_16 */ + { .id = TOP_HDMI_APB_SEL, .sel = 2 }, /* 2: msdcpll_d2 */ + { .id = TOP_SNPS_ETH_250M_SEL, .sel = 1 }, /* 1: ethpll_d2 */ + { .id = TOP_SNPS_ETH_62P4M_PTP_SEL, .sel = 1 }, /* 1: ethpll_d8 */ + { .id = TOP_SNPS_ETH_50M_RMII_SEL, .sel = 1 }, /* 1: ethpll_d10 */ + /* CLK_CFG_17 */ + { .id = TOP_ADSP_SEL, .sel = 8 }, /* 8: adsppll_ck */ + { .id = TOP_AUDIO_LOCAL_BUS_SEL, .sel = 4 }, /* 4: mainpll_d5_d2 */ + { .id = TOP_ASM_H_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */ + { .id = TOP_ASM_L_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */ + /* CLK_CFG_18 */ + { .id = TOP_APLL1_SEL, .sel = 1 }, /* 1: apll1_d4 */ + { .id = TOP_APLL2_SEL, .sel = 1 }, /* 1: apll2_d4 */ + { .id = TOP_APLL3_SEL, .sel = 1 }, /* 1: apll3_d4 */ + { .id = TOP_APLL4_SEL, .sel = 1 }, /* 1: apll4_d4 */ + /* CLK_CFG_19 */ + { .id = TOP_APLL5_SEL, .sel = 1 }, /* 1: apll5_d4 */ + { .id = TOP_I2SO1_SEL, .sel = 1 }, /* 1: apll1_ck */ + { .id = TOP_I2SO2_SEL, .sel = 1 }, /* 1: apll1_ck */ + { .id = TOP_I2SI1_SEL, .sel = 1 }, /* 1: apll1_ck */ + /* CLK_CFG_20 */ + { .id = TOP_I2SI2_SEL, .sel = 1 }, /* 1: apll1_ck */ + { .id = TOP_DPTX_SEL, .sel = 1 }, /* 1: apll1_ck */ + { .id = TOP_AUD_IEC_SEL, .sel = 1 }, /* 1: apll1_ck */ + { .id = TOP_A1SYS_HP_SEL, .sel = 1 }, /* 1: apll1_d4 */ + /* CLK_CFG_21 */ + { .id = TOP_A2SYS_SEL, .sel = 1 }, /* 1: apll2_d4 */ + { .id = TOP_A3SYS_SEL, .sel = 1 }, /* 1: apll3_d4 */ + { .id = TOP_A4SYS_SEL, .sel = 2 }, /* 2: apll4_d4 */ + { .id = TOP_ECC_SEL, .sel = 1 }, /* 1: mainpll_d4_d4 */ + /* CLK_CFG_22 */ + { .id = TOP_SPINOR_SEL, .sel = 3 }, /* 3: univpll_d6_d8 */ + { .id = TOP_ULPOSC_SEL, .sel = 0 }, /* 3: ulposc_ck */ + { .id = TOP_SRCK_SEL, .sel = 0 }, /* 0: ulposc_d10 */ +}; + +enum pll_id { + APMIXED_ARMPLL_LL, + APMIXED_ARMPLL_BL, + APMIXED_CCIPLL, + APMIXED_ETHPLL, + APMIXED_MSDCPLL, + APMIXED_TVDPLL1, + APMIXED_TVDPLL2, + APMIXED_MMPLL, + APMIXED_MAINPLL, + APMIXED_IMGPLL, + APMIXED_UNIVPLL, + APMIXED_ADSPPLL, + APMIXED_APLL1, + APMIXED_APLL2, + APMIXED_APLL3, + APMIXED_APLL4, + APMIXED_APLL5, + APMIXED_MFGPLL, + APMIXED_PLL_MAX +}; + +static const u32 pll_div_rate[] = { + 3800UL * MHz, + 1900 * MHz, + 950 * MHz, + 475 * MHz, + 237500 * KHz, + 0, +}; + +static const struct pll plls[] = { + PLL(APMIXED_ARMPLL_LL, armpll_ll_con0, armpll_ll_con3, + NO_RSTB_SHIFT, 22, armpll_ll_con0, 24, armpll_ll_con1, 0, + pll_div_rate), + PLL(APMIXED_ARMPLL_BL, armpll_bl_con0, armpll_bl_con3, + NO_RSTB_SHIFT, 22, armpll_bl_con0, 24, armpll_bl_con1, 0, + pll_div_rate), + PLL(APMIXED_CCIPLL, ccipll_con0, ccipll_con3, + NO_RSTB_SHIFT, 22, ccipll_con0, 24, ccipll_con1, 0, + pll_div_rate), + PLL(APMIXED_ETHPLL, ethpll_con0, ethpll_con3, + NO_RSTB_SHIFT, 22, ethpll_con0, 24, ethpll_con1, 0, + pll_div_rate), + PLL(APMIXED_MSDCPLL, msdcpll_con0, msdcpll_con3, + NO_RSTB_SHIFT, 22, msdcpll_con0, 24, msdcpll_con1, 0, + pll_div_rate), + PLL(APMIXED_TVDPLL1, tvdpll1_con0, tvdpll1_con3, + NO_RSTB_SHIFT, 22, tvdpll1_con0, 24, tvdpll1_con1, 0, + pll_div_rate), + PLL(APMIXED_TVDPLL2, tvdpll2_con0, tvdpll2_con3, + NO_RSTB_SHIFT, 22, tvdpll2_con0, 24, tvdpll2_con1, 0, + pll_div_rate), + PLL(APMIXED_MMPLL, mmpll_con0, mmpll_con3, + 23, 22, mmpll_con0, 24, mmpll_con1, 0, + pll_div_rate), + PLL(APMIXED_MAINPLL, mainpll_con0, mainpll_con3, + 23, 22, mainpll_con0, 24, mainpll_con1, 0, + pll_div_rate), + PLL(APMIXED_IMGPLL, imgpll_con0, imgpll_con3, + NO_RSTB_SHIFT, 22, imgpll_con0, 24, imgpll_con1, 0, + pll_div_rate), + PLL(APMIXED_UNIVPLL, univpll_con0, univpll_con3, + 23, 22, univpll_con0, 24, univpll_con1, 0, + pll_div_rate), + PLL(APMIXED_ADSPPLL, adsppll_con0, adsppll_con3, + NO_RSTB_SHIFT, 22, adsppll_con0, 24, adsppll_con1, 0, + pll_div_rate), + PLL(APMIXED_APLL1, apll1_con0, apll1_con4, + NO_RSTB_SHIFT, 32, apll1_con0, 24, apll1_con2, 0, + pll_div_rate), + PLL(APMIXED_APLL2, apll2_con0, apll2_con4, + NO_RSTB_SHIFT, 32, apll2_con0, 24, apll2_con2, 0, + pll_div_rate), + PLL(APMIXED_APLL3, apll3_con0, apll3_con4, + NO_RSTB_SHIFT, 32, apll3_con0, 24, apll3_con2, 0, + pll_div_rate), + PLL(APMIXED_APLL4, apll4_con0, apll4_con4, + NO_RSTB_SHIFT, 32, apll4_con0, 24, apll4_con2, 0, + pll_div_rate), + PLL(APMIXED_APLL5, apll5_con0, apll5_con4, + NO_RSTB_SHIFT, 32, apll5_con0, 24, apll5_con2, 0, + pll_div_rate), + PLL(APMIXED_MFGPLL, mfgpll_con0, mfgpll_con3, + NO_RSTB_SHIFT, 22, mfgpll_con0, 24, mfgpll_con1, 0, + pll_div_rate), +}; + +struct rate { + enum pll_id id; + u32 rate; +}; + +static const struct rate rates[] = { + { .id = APMIXED_ARMPLL_LL, .rate = ARMPLL_LL_HZ }, + { .id = APMIXED_ARMPLL_BL, .rate = ARMPLL_BL_HZ }, + { .id = APMIXED_CCIPLL, .rate = CCIPLL_HZ }, + { .id = APMIXED_ETHPLL, .rate = ETHPLL_HZ }, + { .id = APMIXED_MSDCPLL, .rate = MSDCPLL_HZ }, + { .id = APMIXED_TVDPLL1, .rate = TVDPLL1_HZ }, + { .id = APMIXED_TVDPLL2, .rate = TVDPLL2_HZ }, + { .id = APMIXED_MMPLL, .rate = MMPLL_HZ }, + { .id = APMIXED_MAINPLL, .rate = MAINPLL_HZ }, + { .id = APMIXED_IMGPLL, .rate = IMGPLL_HZ }, + { .id = APMIXED_UNIVPLL, .rate = UNIVPLL_HZ }, + { .id = APMIXED_ADSPPLL, .rate = ADSPPLL_HZ }, + { .id = APMIXED_APLL1, .rate = APLL1_HZ }, + { .id = APMIXED_APLL2, .rate = APLL2_HZ }, + { .id = APMIXED_APLL3, .rate = APLL3_HZ }, + { .id = APMIXED_APLL4, .rate = APLL4_HZ }, + { .id = APMIXED_APLL5, .rate = APLL5_HZ }, + { .id = APMIXED_MFGPLL, .rate = MFGPLL_HZ }, +}; + +void pll_set_pcw_change(const struct pll *pll) +{ + setbits32(pll->div_reg, PLL_PCW_CHG); +} + +void mt_pll_init(void) +{ + int i; + + /* enable clock square */ + setbits32(&mtk_apmixed->ap_pll_con0, BIT(2)); + + udelay(PLL_CKSQ_ON_DELAY); + + /* enable clock square1 low-pass filter */ + setbits32(&mtk_apmixed->ap_pll_con0, BIT(1)); + + /* + * BIT(3): 1 for register control; 0 for sleep control + * BIT(8): 1 to enable clock square2; 0 to disable it + */ + clrbits32(&mtk_apmixed->ap_pll_con0, BIT(3) | BIT(8)); + + /* xPLL PWR ON */ + for (i = 0; i < APMIXED_PLL_MAX; i++) + setbits32(plls[i].pwr_reg, PLL_PWR_ON); + + udelay(PLL_PWR_ON_DELAY); + + /* xPLL ISO Disable */ + for (i = 0; i < APMIXED_PLL_MAX; i++) + clrbits32(plls[i].pwr_reg, PLL_ISO); + + udelay(PLL_ISO_DELAY); + + /* disable glitch free if rate < 374MHz */ + for (i = 0; i < ARRAY_SIZE(rates); i++) { + if (rates[i].rate < 374 * MHz) + clrbits32(plls[rates[i].id].reg, GLITCH_FREE_EN); + } + + /* disable mfg_ck_en[20], enable mfg_opp_ck_en[2] */ + clrbits32(&mtk_apmixed->mfgpll_con0, 0x1 << 20); + setbits32(&mtk_apmixed->mfgpll_con1, 0x1 << 2); + + /* xPLL Frequency Set */ + for (i = 0; i < ARRAY_SIZE(rates); i++) + pll_set_rate(&plls[rates[i].id], rates[i].rate); + + /* AUDPLL Tuner Frequency Set */ + write32(&mtk_apmixed->apll1_tuner_con0, read32(&mtk_apmixed->apll1_con3) + 1); + write32(&mtk_apmixed->apll2_tuner_con0, read32(&mtk_apmixed->apll2_con3) + 1); + write32(&mtk_apmixed->apll3_tuner_con0, read32(&mtk_apmixed->apll3_con3) + 1); + write32(&mtk_apmixed->apll4_tuner_con0, read32(&mtk_apmixed->apll4_con3) + 1); + write32(&mtk_apmixed->apll5_tuner_con0, read32(&mtk_apmixed->apll5_con3) + 1); + + /* xPLL Frequency Enable */ + for (i = 0; i < APMIXED_PLL_MAX; i++) { + if (i == APMIXED_APLL5) + setbits32(plls[i].pwr_reg, MT8188_APLL5_EN); + else + setbits32(plls[i].reg, MT8188_PLL_EN); + } + + /* enable univpll analog divider=13 */ + setbits32(&mtk_apmixed->univpll_con0, 0x8d); + + /* wait for PLL stable */ + udelay(PLL_EN_DELAY); + + /* xPLL DIV Enable & RSTB */ + for (i = 0; i < APMIXED_PLL_MAX; i++) { + if (plls[i].rstb_shift != NO_RSTB_SHIFT) { + setbits32(plls[i].reg, PLL_DIV_EN); + setbits32(plls[i].reg, 1 << plls[i].rstb_shift); + } + } + + /* MCUCFG CLKMUX */ + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1); + + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + + /* initialize SPM request */ + setbits32(&mtk_topckgen->clk_scp_cfg_0, 0x3ff); + + /* + * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS! + */ + for (i = 0; i < ARRAY_SIZE(mux_sels); i++) + mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); + + /* turn off unused clock in infra_ao */ + write32(&mt8188_infracfg_ao->module_sw_cg_1_set, 0x00004000); + write32(&mt8188_infracfg_ao->module_sw_cg_2_set, 0xf0003802); + write32(&mt8188_infracfg_ao->module_sw_cg_3_set, 0x30000000); + write32(&mt8188_infracfg_ao->module_sw_cg_4_set, 0x81c20000); +} + +void mt_pll_raise_little_cpu_freq(u32 freq) +{ + /* switch clock source to intermediate clock */ + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M); + + /* disable armpll_ll frequency output */ + clrbits32(plls[APMIXED_ARMPLL_LL].reg, MT8188_PLL_EN); + + /* raise armpll_ll frequency */ + pll_set_rate(&plls[APMIXED_ARMPLL_LL], freq); + + /* enable armpll_ll frequency output */ + setbits32(plls[APMIXED_ARMPLL_LL].reg, MT8188_PLL_EN); + udelay(PLL_EN_DELAY); + + /* switch clock source back to armpll_ll */ + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); +} + +void mt_pll_raise_cci_freq(u32 freq) +{ + /* switch clock source to intermediate clock */ + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_26M); + + /* disable ccipll frequency output */ + clrbits32(plls[APMIXED_CCIPLL].reg, MT8188_PLL_EN); + + /* raise ccipll frequency */ + pll_set_rate(&plls[APMIXED_CCIPLL], freq); + + /* enable ccipll frequency output */ + setbits32(plls[APMIXED_CCIPLL].reg, MT8188_PLL_EN); + udelay(PLL_EN_DELAY); + + /* switch clock source back to ccipll */ + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); +} + +void mt_pll_set_tvd_pll1_freq(u32 freq) +{ + /* disable tvdpll frequency output */ + clrbits32(plls[APMIXED_TVDPLL1].reg, MT8188_PLL_EN); + + /* set tvdpll frequency */ + pll_set_rate(&plls[APMIXED_TVDPLL1], freq); + + /* enable tvdpll frequency output */ + setbits32(plls[APMIXED_TVDPLL1].reg, MT8188_PLL_EN); + udelay(PLL_EN_DELAY); +} + +void edp_mux_set_sel(u32 sel) +{ + mux_set_sel(&muxes[TOP_EDP_SEL], sel); +} + +void mt_pll_set_usb_clock(void) +{ + /* port0 */ + setbits32(&mt8188_pericfg_ao->peri_module_sw_cg_0_clr, BIT(9) | BIT(10)); + setbits32(&mtk_topckgen->clk_misc_cfg_3, BIT(3) | BIT(5)); + + /* port1 sys clk */ + setbits32(&mtk_topckgen->clk_cfg_10_clr, BIT(15)); + setbits32(&mtk_topckgen->clk_cfg_10_set, BIT(8)); + setbits32(&mtk_topckgen->clk_cfg_update1, BIT(9)); + setbits32(&mt8188_pericfg_ao->peri_module_sw_cg_0_clr, BIT(13)); + + /* port1 xhci clk */ + setbits32(&mtk_topckgen->clk_cfg_10_clr, BIT(23)); + setbits32(&mtk_topckgen->clk_cfg_10_set, BIT(16)); + setbits32(&mtk_topckgen->clk_cfg_update1, BIT(10)); + setbits32(&mt8188_pericfg_ao->peri_module_sw_cg_0_clr, BIT(14)); + + setbits32(&mtk_topckgen->clk_misc_cfg_3, BIT(2) | BIT(4)); +} + +u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id) +{ + u32 output, count, clk_dbg_cfg, clk_misc_cfg_0; + u32 multiplier = 1; + + /* backup */ + clk_dbg_cfg = read32(&mtk_topckgen->clk_dbg_cfg); + clk_misc_cfg_0 = read32(&mtk_topckgen->clk_misc_cfg_0); + + /* set up frequency meter */ + if (type == FMETER_ABIST) { + SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg, + CLK_DBG_CFG_ABIST_CK_SEL, id, + CLK_DBG_CFG_CKGEN_CK_SEL, 0, + CLK_DBG_CFG_METER_CK_SEL, 0, + CLK_DBG_CFG_CKGEN_EN, 0); + SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0, + CLK_MISC_CFG_0_METER_DIV, 3); + multiplier = 4; + } else if (type == FMETER_CKGEN) { + SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg, + CLK_DBG_CFG_ABIST_CK_SEL, 0, + CLK_DBG_CFG_CKGEN_CK_SEL, id, + CLK_DBG_CFG_METER_CK_SEL, 1, + CLK_DBG_CFG_CKGEN_EN, 1); + SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0, + CLK_MISC_CFG_0_METER_DIV, 0); + } else { + die("unsupported fmeter type\n"); + } + + /* enable frequency meter */ + write32(&mtk_topckgen->clk26cali_0, 0x80); + + /* set load count = 1024-1 */ + SET32_BITFIELDS(&mtk_topckgen->clk26cali_1, CLK26CALI_1_LOAD_CNT, 0x3ff); + + /* trigger frequency meter */ + SET32_BITFIELDS(&mtk_topckgen->clk26cali_0, CLK26CALI_0_TRIGGER, 1); + + /* wait frequency meter until finished */ + if (wait_us(200, !READ32_BITFIELD(&mtk_topckgen->clk26cali_0, CLK26CALI_0_TRIGGER))) { + count = read32(&mtk_topckgen->clk26cali_1) & 0xffff; + output = (count * 26000) / 1024; /* KHz */ + } else { + printk(BIOS_WARNING, "fmeter timeout\n"); + output = 0; + } + + /* disable frequency meter */ + write32(&mtk_topckgen->clk26cali_0, 0x0000); + + /* restore */ + write32(&mtk_topckgen->clk_dbg_cfg, clk_dbg_cfg); + write32(&mtk_topckgen->clk_misc_cfg_0, clk_misc_cfg_0); + + return output * multiplier; +} |