diff options
Diffstat (limited to 'src/soc/mediatek/mt8183')
| -rw-r--r-- | src/soc/mediatek/mt8183/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/i2c.c | 150 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/addressmap.h | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/i2c.h | 59 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/mt8183.c | 2 |
5 files changed, 217 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 2f44882bb8..2a65c35ea3 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -6,6 +6,7 @@ bootblock-y += ../common/gpio.c gpio.c bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += mt8183.c +bootblock-y += ../common/i2c.c i2c.c bootblock-y += ../common/timer.c bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c @@ -18,6 +19,7 @@ verstage-y += auxadc.c verstage-y += ../common/gpio.c gpio.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += mt8183.c +verstage-y += ../common/i2c.c i2c.c verstage-y += ../common/timer.c verstage-y += ../common/uart.c verstage-y += ../common/wdt.c @@ -36,6 +38,7 @@ romstage-y += ../common/pll.c pll.c romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6358.c romstage-y += ../common/rtc.c rtc.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/timer.c romstage-y += ../common/uart.c romstage-y += ../common/wdt.c @@ -43,6 +46,7 @@ romstage-y += ../common/wdt.c ramstage-y += auxadc.c ramstage-y += ../common/cbmem.c emi.c ramstage-y += ../common/gpio.c gpio.c +ramstage-y += ../common/i2c.c i2c.c ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += ../common/pmic_wrap.c diff --git a/src/soc/mediatek/mt8183/i2c.c b/src/soc/mediatek/mt8183/i2c.c new file mode 100644 index 0000000000..a70c5e175d --- /dev/null +++ b/src/soc/mediatek/mt8183/i2c.c @@ -0,0 +1,150 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <device/mmio.h> +#include <soc/pll.h> +#include <soc/i2c.h> +#include <soc/gpio.h> + +#define I2C_CLK_HZ (UNIVPLL_HZ / 20) + +struct mtk_i2c mtk_i2c_bus_controller[] = { + /* i2c0 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x2000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE), + }, + + /* i2c1 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0xc000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x400), + }, + + /* i2c2 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x4000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x200), + }, + + /* i2c3 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0xa000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x380), + }, + + /* i2c4 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x3000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x80), + }, + + /* i2c5 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x11000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x480), + }, + + /* i2c6 setting */ + { + .i2c_regs = (void *)(I2C_BASE), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x580), + }, +}; + +#define I2C_BUS_NUMBER ARRAY_SIZE(mtk_i2c_bus_controller) + +struct pad_func { + gpio_t gpio; + u8 func; +}; + +#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} + +static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = { + { + PAD_FUNC(SDA0, SDA0), + PAD_FUNC(SCL0, SCL0), + }, + { + PAD_FUNC(SDA1, SDA1), + PAD_FUNC(SCL1, SCL1), + }, + { + PAD_FUNC(SDA2, SDA2), + PAD_FUNC(SCL2, SCL2), + }, + { + PAD_FUNC(SDA3, SDA3), + PAD_FUNC(SCL3, SCL3), + }, + { + PAD_FUNC(SDA4, SDA4), + PAD_FUNC(SCL4, SCL4), + }, + { + PAD_FUNC(SDA5, SDA5), + PAD_FUNC(SCL5, SCL5), + }, + { + PAD_FUNC(SDA6, SDA6), + PAD_FUNC(SCL6, SCL6), + }, +}; + +static void mtk_i2c_set_gpio_pinmux(uint8_t bus) +{ + assert(bus < I2C_BUS_NUMBER); + + const struct pad_func *ptr = i2c_funcs[bus]; + for (size_t i = 0; i < 2; i++) { + gpio_set_mode(ptr[i].gpio, ptr[i].func); + gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP); + } +} + +static void mtk_i2c_speed_init(uint8_t bus) +{ + uint8_t step_div; + const uint8_t clock_div = 5; + const uint8_t sample_div = 1; + uint32_t i2c_freq; + + assert(bus < ARRAY_SIZE(mtk_i2c_bus_controller)); + + /* Calculate i2c frequency */ + step_div = DIV_ROUND_UP(I2C_CLK_HZ, + (400 * KHz * sample_div * 2) * clock_div); + i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2 * clock_div); + assert(sample_div < 8 && step_div < 64 && i2c_freq <= 400 * KHz && + i2c_freq >= 380 * KHz); + + /* Init i2c bus Timing register */ + write32(&mtk_i2c_bus_controller[bus].i2c_regs->timing, + (sample_div - 1) << 8 | (step_div - 1)); + write32(&mtk_i2c_bus_controller[bus].i2c_regs->ltiming, + (sample_div - 1) << 6 | (step_div - 1)); + + /* Init i2c bus clock_div register */ + write32(&mtk_i2c_bus_controller[bus].i2c_regs->clock_div, + clock_div - 1); +} + +void mtk_i2c_bus_init(uint8_t bus) +{ + mtk_i2c_speed_init(bus); + mtk_i2c_set_gpio_pinmux(bus); +} diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index 0f085b2c8d..5a4784d03d 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -36,8 +36,10 @@ enum { DRAMC_CH_BASE = IO_PHYS + 0x00228000, SSPM_SRAM_BASE = IO_PHYS + 0x00400000, SSPM_CFG_BASE = IO_PHYS + 0x00440000, + I2C_DMA_BASE = IO_PHYS + 0x01000080, AUXADC_BASE = IO_PHYS + 0x01001000, UART0_BASE = IO_PHYS + 0x01002000, + I2C_BASE = IO_PHYS + 0x01005000, SPI0_BASE = IO_PHYS + 0x0100A000, SPI1_BASE = IO_PHYS + 0x01010000, SPI2_BASE = IO_PHYS + 0x01012000, diff --git a/src/soc/mediatek/mt8183/include/soc/i2c.h b/src/soc/mediatek/mt8183/include/soc/i2c.h new file mode 100644 index 0000000000..a75b6f002e --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/i2c.h @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_MT8183_I2C_H +#define SOC_MEDIATEK_MT8183_I2C_H + +#include <soc/i2c_common.h> + +/* I2C Register */ +struct mt_i2c_regs { + uint32_t data_port; + uint32_t slave_addr; + uint32_t intr_mask; + uint32_t intr_stat; + uint32_t control; + uint32_t transfer_len; + uint32_t transac_len; + uint32_t delay_len; + uint32_t timing; + uint32_t start; + uint32_t ext_conf; + uint32_t ltiming; + uint32_t hs; + uint32_t io_config; + uint32_t fifo_addr_clr; + uint32_t reserved0[2]; + uint32_t transfer_aux_len; + uint32_t clock_div; + uint32_t time_out; + uint32_t softreset; + uint32_t reserved1[36]; + uint32_t debug_stat; + uint32_t debug_ctrl; + uint32_t reserved2[2]; + uint32_t fifo_stat; + uint32_t fifo_thresh; + uint32_t reserved3[932]; + uint32_t multi_dma; + uint32_t reserved4[2]; + uint32_t rollback; +}; + +check_member(mt_i2c_regs, multi_dma, 0xf8c); + +void mtk_i2c_bus_init(uint8_t bus); + +#endif /* SOC_MEDIATEK_MT8183_I2C_H */ diff --git a/src/soc/mediatek/mt8183/mt8183.c b/src/soc/mediatek/mt8183/mt8183.c index c4419803da..32da3e0ea5 100644 --- a/src/soc/mediatek/mt8183/mt8183.c +++ b/src/soc/mediatek/mt8183/mt8183.c @@ -15,8 +15,10 @@ #include <soc/mt8183.h> #include <soc/wdt.h> +#include <soc/gpio.h> void mt8183_early_init(void) { mtk_wdt_init(); + gpio_set_i2c_eh_rsel(); } |