4 files changed, 159 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc
index 45276835af..cac793fc90 100644
--- a/src/soc/mediatek/mt8183/Makefile.inc
+++ b/src/soc/mediatek/mt8183/Makefile.inc
@@ -46,6 +46,7 @@ romstage-y += ../common/wdt.c
 ramstage-y += auxadc.c
 ramstage-y += ../common/cbmem.c emi.c
 ramstage-y += ../common/ddp.c ddp.c
+ramstage-y += ../common/dsi.c dsi.c
 ramstage-y += ../common/gpio.c gpio.c
 ramstage-y += ../common/i2c.c i2c.c
 ramstage-y += ../common/mmu_operations.c mmu_operations.c
diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/mt8183/dsi.c
new file mode 100644
index 0000000000..daa06caeae
--- /dev/null
+++ b/src/soc/mediatek/mt8183/dsi.c
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <device/mmio.h>
+#include <console/console.h>
+#include <delay.h>
+#include <soc/dsi.h>
+#include <soc/pll.h>
+
+void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes)
+{
+	unsigned int txdiv, txdiv0, txdiv1;
+	u64 pcw;
+
+	if (data_rate >= 2000) {
+		txdiv = 1;
+		txdiv0 = 0;
+		txdiv1 = 0;
+	} else if (data_rate >= 1000) {
+		txdiv = 2;
+		txdiv0 = 1;
+		txdiv1 = 0;
+	} else if (data_rate >= 500) {
+		txdiv = 4;
+		txdiv0 = 2;
+		txdiv1 = 0;
+	} else if (data_rate > 250) {
+		/* Be aware that 250 is a special case that must use txdiv=4. */
+		txdiv = 8;
+		txdiv0 = 3;
+		txdiv1 = 0;
+	} else {
+		/* MIN = 125 */
+		assert(data_rate >= MTK_DSI_DATA_RATE_MIN_MHZ);
+		txdiv = 16;
+		txdiv0 = 4;
+		txdiv1 = 0;
+	}
+
+	clrbits_le32(&mipi_tx->pll_con4, BIT(11) | BIT(10));
+	setbits_le32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_PWR_ON);
+	udelay(30);
+	clrbits_le32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_ISO_EN);
+
+	pcw = (u64)data_rate * (1 << txdiv0) * (1 << txdiv1);
+	pcw <<= 24;
+	pcw /= CLK26M_HZ / MHz;
+
+	write32(&mipi_tx->pll_con0, pcw);
+	clrsetbits_le32(&mipi_tx->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8);
+	udelay(30);
+	setbits_le32(&mipi_tx->pll_con1, RG_DSI_PLL_EN);
+
+	/* BG_LPF_EN / BG_CORE_EN */
+	write32(&mipi_tx->lane_con, 0x3fff0180);
+	udelay(40);
+	write32(&mipi_tx->lane_con, 0x3fff00c0);
+
+	/* Switch OFF each Lane */
+	clrbits_le32(&mipi_tx->d0_sw_ctl_en, DSI_SW_CTL_EN);
+	clrbits_le32(&mipi_tx->d1_sw_ctl_en, DSI_SW_CTL_EN);
+	clrbits_le32(&mipi_tx->d2_sw_ctl_en, DSI_SW_CTL_EN);
+	clrbits_le32(&mipi_tx->d3_sw_ctl_en, DSI_SW_CTL_EN);
+	clrbits_le32(&mipi_tx->ck_sw_ctl_en, DSI_SW_CTL_EN);
+
+	setbits_le32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN);
+}
+
+void mtk_dsi_reset(void)
+{
+	write32(&dsi0->dsi_force_commit,
+		DSI_FORCE_COMMIT_USE_MMSYS | DSI_FORCE_COMMIT_ALWAYS);
+	write32(&dsi0->dsi_con_ctrl, 1);
+	write32(&dsi0->dsi_con_ctrl, 0);
+}
diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h
index bb44f9bb45..c267a1473e 100644
--- a/src/soc/mediatek/mt8183/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h
@@ -51,6 +51,7 @@ enum {
 	IOCFG_RT_BASE		= IO_PHYS + 0x01C50000,
 	IOCFG_RM_BASE		= IO_PHYS + 0x01D20000,
 	IOCFG_RB_BASE		= IO_PHYS + 0x01D30000,
+	MIPITX_BASE             = IO_PHYS + 0x01E50000,
 	IOCFG_LB_BASE		= IO_PHYS + 0x01E70000,
 	IOCFG_LM_BASE		= IO_PHYS + 0x01E80000,
 	IOCFG_BL_BASE		= IO_PHYS + 0x01E90000,
@@ -69,6 +70,7 @@ enum {
 	DISP_AAL0_BASE		= IO_PHYS + 0x04010000,
 	DISP_GAMMA0_BASE	= IO_PHYS + 0x04011000,
 	DISP_DITHER0_BASE	= IO_PHYS + 0x04012000,
+	DSI0_BASE               = IO_PHYS + 0x04014000,
 	DISP_MUTEX_BASE		= IO_PHYS + 0x04016000,
 	SMI_LARB0		= IO_PHYS + 0x04017000,
 	SMI_BASE		= IO_PHYS + 0x04019000,
diff --git a/src/soc/mediatek/mt8183/include/soc/dsi.h b/src/soc/mediatek/mt8183/include/soc/dsi.h
new file mode 100644
index 0000000000..8813f94982
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/dsi.h
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_MEDIATEK_MT8183_DSI_H
+#define SOC_MEDIATEK_MT8183_DSI_H
+
+#include <soc/dsi_common.h>
+
+/* DSI features */
+#define MTK_DSI_MIPI_RATIO_NUMERATOR 100
+#define MTK_DSI_MIPI_RATIO_DENOMINATOR 100
+#define MTK_DSI_DATA_RATE_MIN_MHZ 125
+#define MTK_DSI_HAVE_SIZE_CON 1
+#define PIXEL_STREAM_CUSTOM_HEADER 0xb
+
+/* MIPITX is SOC specific and cannot live in common. */
+
+/* MIPITX_REG */
+struct mipi_tx_regs {
+	u32 reserved0[3];
+	u32 lane_con;
+	u32 reserved1[6];
+	u32 pll_pwr;
+	u32 pll_con0;
+	u32 pll_con1;
+	u32 pll_con2;
+	u32 pll_con3;
+	u32 pll_con4;
+	u32 reserved2[65];
+	u32 d2_sw_ctl_en;
+	u32 reserved3[63];
+	u32 d0_sw_ctl_en;
+	u32 reserved4[56];
+	u32 ck_ckmode_en;
+	u32 reserved5[6];
+	u32 ck_sw_ctl_en;
+	u32 reserved6[63];
+	u32 d1_sw_ctl_en;
+	u32 reserved7[63];
+	u32 d3_sw_ctl_en;
+};
+
+check_member(mipi_tx_regs, pll_con4, 0x3c);
+check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544);
+static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE;
+
+/* Register values */
+#define DSI_CK_CKMODE_EN	BIT(0)
+#define DSI_SW_CTL_EN		BIT(0)
+#define AD_DSI_PLL_SDM_PWR_ON	BIT(0)
+#define AD_DSI_PLL_SDM_ISO_EN	BIT(1)
+
+#define RG_DSI_PLL_EN		BIT(4)
+#define RG_DSI_PLL_POSDIV	(0x7 << 8)
+
+#endif