4 files changed, 0 insertions, 11 deletions
diff --git a/src/soc/mediatek/mt8173/da9212.c b/src/soc/mediatek/mt8173/da9212.c
index 5028f18792..2b118bfa0c 100644
--- a/src/soc/mediatek/mt8173/da9212.c
+++ b/src/soc/mediatek/mt8173/da9212.c
@@ -47,7 +47,6 @@ static void da9212_hw_init(uint8_t i2c_num, unsigned char variant_id)
 
 	if (ret)
 		printk(BIOS_ERR, "%s failed\n", __func__);
-
 }
 
 void da9212_probe(uint8_t i2c_num)
diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c
index 10d03e0c8e..e58ea53bbd 100644
--- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c
+++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c
@@ -154,7 +154,6 @@ static void mem_pll_init_phase_sync(u32 channel)
 static void pll_phase_adjust(u32 channel, struct mem_pll *mempll, int reg_offs)
 {
 	switch (mempll->phase) {
-
 	case MEMPLL_INIT:
 		/* initial phase: zero out RG_MEPLL(2,3,4)_(REF_DL,FB)_DL */
 		clrbits32(&ch[channel].ddrphy_regs->mempll[reg_offs],
@@ -189,7 +188,6 @@ static void pll_phase_check(u32 channel, struct mem_pll *mempll, int idx)
 		      (idx + 2), mempll->phase, one_count, zero_count);
 
 	switch (mempll->phase) {
-
 	case MEMPLL_INIT:
 		if ((one_count - zero_count) > JMETER_COUNT_N) {
 			/* REF lag FBK */
@@ -243,7 +241,6 @@ static void mem_pll_phase_cali(u32 channel)
 			     JMETER_COUNT << JMETER_COUNTER_SHIFT);
 
 	while (1) {
-
 		for (i = 0; i < 3; i++) {
 			if (!mempll[i].done) {
 				pll_phase_adjust(channel, &mempll[i], (i + 2) * 3);
@@ -317,7 +314,6 @@ void mem_pll_init(const struct mt8173_sdram_params *sdram_params)
 	udelay(100);
 
 	for (channel = 0; channel < CHANNEL_NUM; channel++) {
-
 		/* mempll_bias_en */
 		write32(&ch[channel].ddrphy_regs->mempll[3], 0xd << 28 |
 							     0x1 << 6);
diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c
index fc5c58c0c6..b9f11a0e5a 100644
--- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c
+++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c
@@ -751,7 +751,6 @@ void tx_delay_for_wrleveling(u32 channel,
 	max_taps = MAX_DQDLY_TAPS - 1;
 
 	for (i = 0; i < DATA_WIDTH_32BIT; i++) {
-
 		index = i / DQS_BIT_NUMBER;
 
 		if (i % DQS_BIT_NUMBER == 0)
@@ -823,7 +822,6 @@ static void set_tx_dly_factor(u32 channel, u32 curr_val, u8 type)
 		value += (curr_val << (4 * i));
 
 	switch (type) {
-
 	case TX_DQS:
 		write32(&ch[channel].ddrphy_regs->padctl3, value);
 		break;
@@ -979,7 +977,6 @@ void perbit_window_cal(u32 channel, u8 type)
 
 	/* delay DQ from 0 to 15 to get the setup time */
 	for (dly = FIRST_DQ_DELAY; dly < MAX_DQDLY_TAPS; dly++) {
-
 		set_dly_factor(channel, STAGE_SETUP, type, dly);
 		err_value = dram_k_perbit(channel);
 
@@ -1015,7 +1012,6 @@ void perbit_window_cal(u32 channel, u8 type)
 	/* delay DQS to get the hold time, dq_dly = dqs_dly = 0 is counted */
 	/* when we delay dq, so we set first dqs delay to 1 */
 	for (dly = (FIRST_DQS_DELAY + 1); dly < max_dqs_taps; dly++) {
-
 		set_dly_factor(channel, STAGE_HOLD, type, dly);
 		err_value = dram_k_perbit(channel);
 
diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c
index 2186c063c1..f9a4629ca5 100644
--- a/src/soc/mediatek/mt8173/mt6391.c
+++ b/src/soc/mediatek/mt8173/mt6391.c
@@ -78,7 +78,6 @@ void mt6391_configure_ldo(enum ldo_power ldo, enum ldo_voltage vsel)
 
 	pwrap_write_field(addr, vsel, 0x7, 5);
 	pwrap_write_field(PMIC_RG_DIGLDO_CON5 + ldo * 2, 1, 1, 15);
-
 }
 
 void mt6391_enable_reset_when_ap_resets(void)
@@ -362,7 +361,6 @@ static void mt6391_init_setting(void)
 	pwrap_write_field(PMIC_RG_ANALDO_CON0, 0x3, 0x3, 3);
 	/* For low power, VIO18 set sleep_en to HW mode */
 	pwrap_write_field(PMIC_RG_VIO18_CON18, 0x1, 0x1, 8);
-
 }
 
 static void mt6391_default_buck_voltage(void)