aboutsummaryrefslogtreecommitdiff
path: root/src/soc/mediatek/mt8173/pll.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/mediatek/mt8173/pll.c')
-rw-r--r--src/soc/mediatek/mt8173/pll.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c
index d54538d91d..1366bb5888 100644
--- a/src/soc/mediatek/mt8173/pll.c
+++ b/src/soc/mediatek/mt8173/pll.c
@@ -467,8 +467,6 @@ void mt_pll_post_init(void)
clrbits_le32(&mt8173_infracfg->top_ckdiv1, 0x3ff);
/* select ARMPLL */
- /* TODO: possibly raise ARMPLL frequency here */
- /* NOTICE: raise Vproc voltage before raise ARMPLL frequency */
write32(&mt8173_infracfg->top_ckmuxsel, (1 << 2) | 1);
}
@@ -506,6 +504,10 @@ void mt_pll_set_aud_div(u32 rate)
}
}
+void mt_pll_raise_ca53_freq(u32 freq) {
+ pll_set_rate(&plls[APMIXED_ARMCA7PLL], freq); /* freq in Hz */
+}
+
void mt_mem_pll_config_pre(const struct mt8173_sdram_params *sdram_params)
{
u32 mpll_sdm_pcw_20_0 = 0xF13B1;