diff options
Diffstat (limited to 'src/soc/mediatek/mt8173/include')
| -rw-r--r-- | src/soc/mediatek/mt8173/include/soc/addressmap.h | 1 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/include/soc/ddp.h | 27 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/include/soc/dsi.h | 162 |
3 files changed, 183 insertions, 7 deletions
diff --git a/src/soc/mediatek/mt8173/include/soc/addressmap.h b/src/soc/mediatek/mt8173/include/soc/addressmap.h index cab127be75..cc1b39d67c 100644 --- a/src/soc/mediatek/mt8173/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8173/include/soc/addressmap.h @@ -64,6 +64,7 @@ enum { DISP_RDMA2_BASE = IO_PHYS + 0x4010000, DISP_COLOR0_BASE = IO_PHYS + 0x4013000, DISP_COLOR1_BASE = IO_PHYS + 0x4014000, + DISP_SPLIT1_BASE = IO_PHYS + 0x4019000, DISP_UFOE_BASE = IO_PHYS + 0x401A000, DSI0_BASE = IO_PHYS + 0x401B000, DSI1_BASE = IO_PHYS + 0x401C000, diff --git a/src/soc/mediatek/mt8173/include/soc/ddp.h b/src/soc/mediatek/mt8173/include/soc/ddp.h index 9846b1ad40..20e356a909 100644 --- a/src/soc/mediatek/mt8173/include/soc/ddp.h +++ b/src/soc/mediatek/mt8173/include/soc/ddp.h @@ -140,6 +140,7 @@ struct mmsys_cfg_regs { u32 hdmi_en; }; +check_member(mmsys_cfg_regs, mmsys_sw1_rst_b, 0x144); check_member(mmsys_cfg_regs, hdmi_en, 0x904); static struct mmsys_cfg_regs * const mmsys_cfg = (void *) MMSYS_BASE; @@ -206,7 +207,20 @@ enum { OVL0_MOUT_EN_COLOR0 = BIT(0), OD_MOUT_EN_RDMA0 = BIT(0), UFOE_MOUT_EN_DSI0 = BIT(0), - COLOR0_SEL_IN_OVL0 = BIT(0), + UFOE_MOUT_EN_SPLIT1 = BIT(1), +}; + +enum { + COLOR0_SEL_IN_OVL0 = 1, + DSI0_SEL_IN_UFOE = 0, + DSI0_SEL_IN_SPLIT1 = 1, + DSI1_SEL_IN_SPLIT1 = 0, +}; + +/* MMSYS_SW1_RST_B */ +enum { + MMSYS_SW1_RST_DSI0_B = BIT(2), + MMSYS_SW1_RST_DSI1_B = BIT(3), }; struct disp_mutex_regs { @@ -386,8 +400,15 @@ static struct disp_ufoe_regs * const disp_ufoe = (void *)DISP_UFOE_BASE; enum { UFO_BYPASS = BIT(2), + UFO_LR = BIT(3) | BIT(0), }; +struct disp_split_regs { + u32 start; +}; + +static struct disp_split_regs * const disp_split = (void *)DISP_SPLIT1_BASE; + struct disp_color_regs { u8 reserved0[1024]; u32 cfg_main; @@ -426,7 +447,7 @@ enum OVL_INPUT_FORMAT { OVL_INFMT_ABGR8888 = OVL_INFMT_ARGB8888 + OVL_COLOR_BASE, }; -void mtk_ddp_init(void); -void mtk_ddp_mode_set(const struct edid *edid); +void mtk_ddp_init(bool dual_dsi_mode); +void mtk_ddp_mode_set(const struct edid *edid, bool dual_dsi_mode); #endif diff --git a/src/soc/mediatek/mt8173/include/soc/dsi.h b/src/soc/mediatek/mt8173/include/soc/dsi.h index 73f4425684..68f45d1144 100644 --- a/src/soc/mediatek/mt8173/include/soc/dsi.h +++ b/src/soc/mediatek/mt8173/include/soc/dsi.h @@ -71,21 +71,45 @@ struct dsi_regs { u32 dsi_hbp_wc; u32 dsi_hfp_wc; u32 dsi_bllp_wc; - u8 reserved2[4]; + u32 dsi_cmdq_size; u32 dsi_hstx_cklp_wc; - u8 reserved3[156]; + u8 reserved2[156]; u32 dsi_phy_lccon; u32 dsi_phy_ld0con; - u8 reserved4[4]; + u8 reserved3[4]; u32 dsi_phy_timecon0; u32 dsi_phy_timecon1; u32 dsi_phy_timecon2; u32 dsi_phy_timecon3; + u8 reserved4[16]; + u32 dsi_vm_cmd_con; + u8 reserved5[204]; + u32 dsi_cmdq0; }; check_member(dsi_regs, dsi_phy_lccon, 0x104); check_member(dsi_regs, dsi_phy_timecon3, 0x11c); +check_member(dsi_regs, dsi_vm_cmd_con, 0x130); +check_member(dsi_regs, dsi_cmdq0, 0x200); static struct dsi_regs * const dsi0 = (void *)DSI0_BASE; +static struct dsi_regs * const dsi1 = (void *)DSI1_BASE; + +/* DSI_INTSTA */ +enum { + LPRX_RD_RDY_INT_FLAG = BIT(0), + CMD_DONE_INT_FLAG = BIT(1), + TE_RDY_INT_FLAG = BIT(2), + VM_DONE_INT_FLAG = BIT(3), + EXT_TE_RDY_INT_FLAG = BIT(4), + DSI_BUSY = BIT(31), +}; + +/* DSI_CON_CTRL */ +enum { + DSI_RESET = BIT(0), + DSI_EN = BIT(1), + DSI_DUAL = BIT(4), +}; /* DSI_MODE_CTRL */ enum { @@ -108,6 +132,11 @@ enum { PACKED_PS_24BIT_RGB888 = (3 << 16) }; +/* DSI_CMDQ_SIZE */ +enum { + CMDQ_SIZE = 0x3f, +}; + /* DSI_PHY_LCCON */ enum { LC_HS_TX_EN = BIT(0), @@ -148,6 +177,23 @@ enum { CLK_HS_EXIT = (0xf << 16) }; +/* DSI_VM_CMD_CON */ +enum { + VM_CMD_EN = BIT(0), + TS_VFP_EN = BIT(5), +}; + +/* DSI_CMDQ0 */ +enum { + CONFIG = (0xff << 0), + SHORT_PACKET = 0, + LONG_PACKET = 2, + BTA = BIT(2), + DATA_ID = (0xff << 8), + DATA_0 = (0xff << 16), + DATA_1 = (0xff << 24), +}; + /* MIPITX_REG */ struct mipi_tx_regs { u32 dsi_con; @@ -182,6 +228,7 @@ check_member(mipi_tx_regs, dsi_top_con, 0x40); check_member(mipi_tx_regs, dsi_pll_pwr, 0x68); static struct mipi_tx_regs * const mipi_tx0 = (void *)MIPI_TX0_BASE; +static struct mipi_tx_regs * const mipi_tx1 = (void *)MIPI_TX0_BASE; /* MIPITX_DSI0_CON */ enum { @@ -276,6 +323,7 @@ struct lvds_tx1_regs { }; static struct lvds_tx1_regs * const lvds_tx1 = (void *)(MIPI_TX0_BASE + 0x800); +static struct lvds_tx1_regs * const lvds_tx2 = (void *)(MIPI_TX1_BASE + 0x800); /* LVDS_VOPLL_CTRL3 */ enum { @@ -288,8 +336,114 @@ enum { RG_DA_LVDSTX_PWR_ON = BIT(9) }; +/* MIPI DSI Processor-to-Peripheral transaction types */ +enum { + MIPI_DSI_V_SYNC_START = 0x01, + MIPI_DSI_V_SYNC_END = 0x11, + MIPI_DSI_H_SYNC_START = 0x21, + MIPI_DSI_H_SYNC_END = 0x31, + + MIPI_DSI_COLOR_MODE_OFF = 0x02, + MIPI_DSI_COLOR_MODE_ON = 0x12, + MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22, + MIPI_DSI_TURN_ON_PERIPHERAL = 0x32, + + MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03, + MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13, + MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23, + + MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04, + MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14, + MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24, + + MIPI_DSI_DCS_SHORT_WRITE = 0x05, + MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15, + + MIPI_DSI_DCS_READ = 0x06, + + MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, + + MIPI_DSI_END_OF_TRANSMISSION = 0x08, + + MIPI_DSI_NULL_PACKET = 0x09, + MIPI_DSI_BLANKING_PACKET = 0x19, + MIPI_DSI_GENERIC_LONG_WRITE = 0x29, + MIPI_DSI_DCS_LONG_WRITE = 0x39, + + MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c, + + MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d, + MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d, + + MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e, + MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e, + MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e, + MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e, +}; + +/* MIPI DSI Peripheral-to-Processor transaction types */ +enum { + MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02, + MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08, + MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11, + MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12, + MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a, + MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c, + MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21, + MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22, +}; + +/* MIPI DCS commands */ +enum { + MIPI_DCS_NOP = 0x00, + MIPI_DCS_SOFT_RESET = 0x01, + MIPI_DCS_GET_DISPLAY_ID = 0x04, + MIPI_DCS_GET_RED_CHANNEL = 0x06, + MIPI_DCS_GET_GREEN_CHANNEL = 0x07, + MIPI_DCS_GET_BLUE_CHANNEL = 0x08, + MIPI_DCS_GET_DISPLAY_STATUS = 0x09, + MIPI_DCS_GET_POWER_MODE = 0x0A, + MIPI_DCS_GET_ADDRESS_MODE = 0x0B, + MIPI_DCS_GET_PIXEL_FORMAT = 0x0C, + MIPI_DCS_GET_DISPLAY_MODE = 0x0D, + MIPI_DCS_GET_SIGNAL_MODE = 0x0E, + MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F, + MIPI_DCS_ENTER_SLEEP_MODE = 0x10, + MIPI_DCS_EXIT_SLEEP_MODE = 0x11, + MIPI_DCS_ENTER_PARTIAL_MODE = 0x12, + MIPI_DCS_ENTER_NORMAL_MODE = 0x13, + MIPI_DCS_EXIT_INVERT_MODE = 0x20, + MIPI_DCS_ENTER_INVERT_MODE = 0x21, + MIPI_DCS_SET_GAMMA_CURVE = 0x26, + MIPI_DCS_SET_DISPLAY_OFF = 0x28, + MIPI_DCS_SET_DISPLAY_ON = 0x29, + MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A, + MIPI_DCS_SET_PAGE_ADDRESS = 0x2B, + MIPI_DCS_WRITE_MEMORY_START = 0x2C, + MIPI_DCS_WRITE_LUT = 0x2D, + MIPI_DCS_READ_MEMORY_START = 0x2E, + MIPI_DCS_SET_PARTIAL_AREA = 0x30, + MIPI_DCS_SET_SCROLL_AREA = 0x33, + MIPI_DCS_SET_TEAR_OFF = 0x34, + MIPI_DCS_SET_TEAR_ON = 0x35, + MIPI_DCS_SET_ADDRESS_MODE = 0x36, + MIPI_DCS_SET_SCROLL_START = 0x37, + MIPI_DCS_EXIT_IDLE_MODE = 0x38, + MIPI_DCS_ENTER_IDLE_MODE = 0x39, + MIPI_DCS_SET_PIXEL_FORMAT = 0x3A, + MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C, + MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E, + MIPI_DCS_SET_TEAR_SCANLINE = 0x44, + MIPI_DCS_GET_SCANLINE = 0x45, + MIPI_DCS_READ_DDB_START = 0xA1, + MIPI_DCS_READ_DDB_CONTINUE = 0xA8, +}; + int mtk_dsi_init(u32 mode_flags, enum mipi_dsi_pixel_format format, u32 lanes, - const struct edid *edid); + bool dual_dsi_mode, const struct edid *edid); void mtk_dsi_pin_drv_ctrl(void); #endif |