2 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8173/include/soc/mt6391.h b/src/soc/mediatek/mt8173/include/soc/mt6391.h
index 392ad634a7..c2a2ef39d5 100644
--- a/src/soc/mediatek/mt8173/include/soc/mt6391.h
+++ b/src/soc/mediatek/mt8173/include/soc/mt6391.h
@@ -98,6 +98,7 @@ enum{
 	PMIC_RG_VCA15_CON9 = 0x0226,
 	PMIC_RG_VCA15_CON10 = 0x0228,
 	PMIC_RG_VCA15_CON11 = 0x022A,
+	PMIC_RG_VCA15_CON12 = 0x022C,
 	PMIC_RG_VCA15_CON18 = 0x0238,
 	PMIC_RG_VSRMCA15_CON5 = 0x0244,
 	PMIC_RG_VSRMCA15_CON6 = 0x0246,
@@ -291,6 +292,7 @@ enum ldo_voltage {
 /*
  * PMIC Exported Function
  */
+int mt6391_configure_ca53_voltage(int uv);
 void mt6391_configure_ldo(enum ldo_power ldo, enum ldo_voltage vsel);
 u32 mt6391_read(u16 reg, u32 mask, u32 shift);
 void mt6391_write(u16 reg, u16 val, u32 mask, u32 shift);
diff --git a/src/soc/mediatek/mt8173/include/soc/pll.h b/src/soc/mediatek/mt8173/include/soc/pll.h
index 6d38bb3447..9b3cca33e7 100644
--- a/src/soc/mediatek/mt8173/include/soc/pll.h
+++ b/src/soc/mediatek/mt8173/include/soc/pll.h
@@ -286,6 +286,7 @@ void mt_pll_post_init(void);
 void mt_pll_init(void);
 void mt_pll_set_aud_div(u32 rate);
 void mt_pll_enable_ssusb_clk(void);
+void mt_pll_raise_ca53_freq(u32 freq);
 void mt_mem_pll_set_clk_cfg(void);
 void mt_mem_pll_config_pre(const struct mt8173_sdram_params *sdram_params);
 void mt_mem_pll_config_post(void);