diff options
Diffstat (limited to 'src/soc/mediatek/mt8173/include/soc/ddp.h')
-rw-r--r-- | src/soc/mediatek/mt8173/include/soc/ddp.h | 138 |
1 files changed, 3 insertions, 135 deletions
diff --git a/src/soc/mediatek/mt8173/include/soc/ddp.h b/src/soc/mediatek/mt8173/include/soc/ddp.h index 2f154ddb67..dbac5f7fb9 100644 --- a/src/soc/mediatek/mt8173/include/soc/ddp.h +++ b/src/soc/mediatek/mt8173/include/soc/ddp.h @@ -13,10 +13,11 @@ * GNU General Public License for more details. */ -#ifndef _DDP_REG_H_ -#define _DDP_REG_H_ +#ifndef _MT8173_SOC_DDP_H_ +#define _MT8173_SOC_DDP_H_ #include <soc/addressmap.h> +#include <soc/ddp_common.h> #include <types.h> struct mmsys_cfg_regs { @@ -254,100 +255,6 @@ enum { MUTEX_MOD_DISP_UFOE | MUTEX_MOD_DISP_OD, }; -struct disp_ovl_regs { - u32 sta; - u32 inten; - u32 intsta; - u32 en; - u32 trig; - u32 rst; - u8 reserved0[8]; - u32 roi_size; - u32 datapath_con; - u32 roi_bgclr; - u32 src_con; - struct { - u32 con; - u32 srckey; - u32 src_size; - u32 offset; - u32 reserved0; - u32 pitch; - u32 reserved1[2]; - } layer[4]; - u8 reserved8[16]; - struct { - u32 ctrl; - u32 mem_start_trig; - u32 mem_gmc_setting; - u32 mem_slow_con; - u32 fifo_ctrl; - u8 reserved[12]; - } rdma[4]; - u8 reserved12[148]; - u32 debug_mon_sel; - u8 reserved13[8]; - u32 rdma_mem_gmc_setting2[4]; - u8 reserved14[16]; - u32 dummy; - u8 reserved15[60]; - u32 flow_ctrl_dbg; - u32 addcon_dbg; - u32 outmux_dbg; - u32 rdma_dbg[4]; - u8 reserved16[3300]; - u32 l0_addr; - u8 reserved17[28]; - u32 l1_addr; - u8 reserved18[28]; - u32 l2_addr; - u8 reserved19[28]; - u32 l3_addr; -}; - -check_member(disp_ovl_regs, l3_addr, 0xFA0); -static struct disp_ovl_regs *const disp_ovl[2] = { - (void *)DIS_OVL0_BASE, (void *)DIS_OVL1_BASE -}; - -struct disp_rdma_regs { - u32 int_enable; - u32 int_status; - u8 reserved0[8]; - u32 global_con; - u32 size_con_0; - u32 size_con_1; - u32 target_line; - u8 reserved1[4]; - u32 mem_con; - u32 mem_start_addr; - u32 mem_src_pitch; - u32 mem_gmc_setting_0; - u32 mem_slow_con; - u32 mem_gmc_setting_1; - u8 reserved2[4]; - u32 fifo_con; - u8 reserved3[16]; - u32 cf[3][3]; - u32 cf_pre_add[3]; - u32 cf_post_add[3]; - u32 dummy; - u32 debug_out_sel; -}; - -enum { - RDMA_ENGINE_EN = BIT(0), - RDMA_FIFO_UNDERFLOW_EN = BIT(31), - RDMA_MEM_GMC = 0x40402020, -}; - -check_member(disp_rdma_regs, debug_out_sel, 0x94); -static struct disp_rdma_regs *const disp_rdma[3] = { - (void *)DISP_RDMA0_BASE, - (void *)DISP_RDMA1_BASE, - (void *)DISP_RDMA2_BASE -}; - struct disp_od_regs { u32 en; u32 reset; @@ -407,45 +314,6 @@ enum { UFO_LR = BIT(3) | BIT(0), }; -struct disp_color_regs { - u8 reserved0[1024]; - u32 cfg_main; - u8 reserved1[2044]; - u32 start; - u8 reserved2[76]; - u32 width; - u32 height; -}; - -check_member(disp_color_regs, cfg_main, 0x400); -check_member(disp_color_regs, start, 0xC00); -check_member(disp_color_regs, width, 0xC50); -check_member(disp_color_regs, height, 0xC54); -static struct disp_color_regs *const disp_color[2] = { - (void *)DISP_COLOR0_BASE, (void *)DISP_COLOR1_BASE -}; - -enum { - COLOR_BYPASS_ALL = BIT(7), - COLOR_SEQ_SEL = BIT(13), -}; - -enum OVL_INPUT_FORMAT { - OVL_INFMT_RGB565 = 0, - OVL_INFMT_RGB888 = 1, - OVL_INFMT_RGBA8888 = 2, - OVL_INFMT_ARGB8888 = 3, - OVL_INFMT_UYVY = 4, - OVL_INFMT_YUYV = 5, - OVL_INFMT_UNKNOWN = 16, - - OVL_COLOR_BASE = 30, - OVL_INFMT_BGR565 = OVL_INFMT_RGB565 + OVL_COLOR_BASE, - OVL_INFMT_BGR888 = OVL_INFMT_RGB888 + OVL_COLOR_BASE, - OVL_INFMT_BGRA8888 = OVL_INFMT_RGBA8888 + OVL_COLOR_BASE, - OVL_INFMT_ABGR8888 = OVL_INFMT_ARGB8888 + OVL_COLOR_BASE, -}; - void mtk_ddp_init(void); void mtk_ddp_mode_set(const struct edid *edid); |