diff options
Diffstat (limited to 'src/soc/mediatek/common')
| -rw-r--r-- | src/soc/mediatek/common/Kconfig | 5 | ||||
| -rw-r--r-- | src/soc/mediatek/common/include/soc/wdt.h | 1 | ||||
| -rw-r--r-- | src/soc/mediatek/common/wdt.c | 5 |
3 files changed, 10 insertions, 1 deletions
diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig index 543bc02d13..29cd2109f9 100644 --- a/src/soc/mediatek/common/Kconfig +++ b/src/soc/mediatek/common/Kconfig @@ -29,4 +29,9 @@ config MEMORY_TEST This option enables memory basic compare test to verify the DRAM read or write is as expected. +config CLEAR_WDT_MODE_REG + bool + help + Enable this option to clear WTD mode register explicitly. + endif diff --git a/src/soc/mediatek/common/include/soc/wdt.h b/src/soc/mediatek/common/include/soc/wdt.h index 44ab5c7700..5847d4953f 100644 --- a/src/soc/mediatek/common/include/soc/wdt.h +++ b/src/soc/mediatek/common/include/soc/wdt.h @@ -21,6 +21,7 @@ struct mtk_wdt_regs { /* WDT_MODE */ enum { MTK_WDT_MODE_KEY = 0x22000000, + MTK_WDT_CLR_STATUS = 0x230001FF, MTK_WDT_MODE_DUAL_MODE = 1 << 6, MTK_WDT_MODE_IRQ = 1 << 3, MTK_WDT_MODE_EXTEN = 1 << 2, diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c index e9edb48ef5..44a9ce50b6 100644 --- a/src/soc/mediatek/common/wdt.c +++ b/src/soc/mediatek/common/wdt.c @@ -9,9 +9,12 @@ int mtk_wdt_init(void) { uint32_t wdt_sta; - /* Write Mode register will clear status register */ + /* Writing mode register will clear status register */ wdt_sta = read32(&mtk_wdt->wdt_status); + if (CONFIG(CLEAR_WDT_MODE_REG)) + write32(&mtk_wdt->wdt_mode, MTK_WDT_CLR_STATUS); + printk(BIOS_INFO, "WDT: Last reset was "); if (wdt_sta & MTK_WDT_STA_HW_RST) { printk(BIOS_INFO, "hardware watchdog\n"); |