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-rw-r--r--src/soc/mediatek/common/include/soc/pll_common.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h
index d9ba2308e9..ae6ad64ded 100644
--- a/src/soc/mediatek/common/include/soc/pll_common.h
+++ b/src/soc/mediatek/common/include/soc/pll_common.h
@@ -3,6 +3,7 @@
#ifndef SOC_MEDIATEK_PLL_COMMON_H
#define SOC_MEDIATEK_PLL_COMMON_H
+#include <device/mmio.h>
#include <soc/addressmap.h>
#include <types.h>
@@ -54,6 +55,15 @@ struct pll {
.div_rate = _div_rate, \
}
+/* every PLL can share the same POWER_EN/ISO_EN/EN bits, use the common BITFIELD macro */
+DEFINE_BIT(PLL_ENABLE, 0)
+
+DEFINE_BIT(PLL_POWER_ENABLE, 0)
+DEFINE_BIT(PLL_ISO_ENABLE, 1)
+DEFINE_BITFIELD(PLL_POWER_ISO_ENABLE, 1, 0)
+
+DEFINE_BITFIELD(PLL_CON1, 31, 0)
+
void pll_set_pcw_change(const struct pll *pll);
void mux_set_sel(const struct mux *mux, u32 sel);
int pll_set_rate(const struct pll *pll, u32 rate);