diff options
Diffstat (limited to 'src/soc/mediatek/common')
| -rw-r--r-- | src/soc/mediatek/common/include/soc/wdt.h | 53 | ||||
| -rw-r--r-- | src/soc/mediatek/common/wdt.c | 63 |
2 files changed, 116 insertions, 0 deletions
diff --git a/src/soc/mediatek/common/include/soc/wdt.h b/src/soc/mediatek/common/include/soc/wdt.h new file mode 100644 index 0000000000..a15434c70d --- /dev/null +++ b/src/soc/mediatek/common/include/soc/wdt.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_COMMON_WDT_H +#define SOC_MEDIATEK_COMMON_WDT_H + +#include <stdint.h> + +struct mtk_wdt_regs { + u32 wdt_mode; + u32 wdt_length; + u32 wdt_restart; + u32 wdt_status; + u32 wdt_interval; + u32 wdt_swrst; + u32 wdt_swsysrst; + u32 reserved[9]; + u32 wdt_debug_ctrl; +}; + +/* WDT_MODE */ +enum { + MTK_WDT_MODE_KEY = 0x22000000, + MTK_WDT_MODE_DUAL_MODE = 1 << 6, + MTK_WDT_MODE_IRQ = 1 << 3, + MTK_WDT_MODE_EXTEN = 1 << 2, + MTK_WDT_MODE_EXT_POL = 1 << 1, + MTK_WDT_MODE_ENABLE = 1 << 0 +}; + +/* WDT_RESET */ +enum { + MTK_WDT_SWRST_KEY = 0x1209, + MTK_WDT_STA_SPM_RST = 1 << 1, + MTK_WDT_STA_SW_RST = 1 << 30, + MTK_WDT_STA_HW_RST = 1 << 31 +}; + +int mtk_wdt_init(void); + +#endif /* SOC_MEDIATEK_COMMON_WDT_H */ diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c new file mode 100644 index 0000000000..c2617531a6 --- /dev/null +++ b/src/soc/mediatek/common/wdt.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <reset.h> +#include <soc/addressmap.h> +#include <soc/wdt.h> +#include <vendorcode/google/chromeos/chromeos.h> + +static struct mtk_wdt_regs *const mtk_wdt = (void *)RGU_BASE; + +int mtk_wdt_init(void) +{ + uint32_t wdt_sta; + + /* Write Mode register will clear status register */ + wdt_sta = read32(&mtk_wdt->wdt_status); + + printk(BIOS_INFO, "WDT: Last reset was "); + if (wdt_sta & MTK_WDT_STA_HW_RST) { + printk(BIOS_INFO, "hardware watchdog\n"); + mark_watchdog_tombstone(); + } else if (wdt_sta & MTK_WDT_STA_SW_RST) + printk(BIOS_INFO, "normal software reboot\n"); + else if (wdt_sta & MTK_WDT_STA_SPM_RST) + printk(BIOS_INFO, "SPM reboot\n"); + else if (!wdt_sta) + printk(BIOS_INFO, "cold boot\n"); + else + printk(BIOS_INFO, "unexpected reset type: %#.8x\n", wdt_sta); + + /* Config watchdog reboot mode: + * Clearing bits: + * DUAL_MODE & IRQ: trigger reset instead of irq then reset. + * EXT_POL: select watchdog output signal as active low. + * ENABLE: disable watchdog on initialization. + * Setting bit EXTEN to enable watchdog output. + */ + clrsetbits_le32(&mtk_wdt->wdt_mode, + MTK_WDT_MODE_DUAL_MODE | MTK_WDT_MODE_IRQ | + MTK_WDT_MODE_EXT_POL | MTK_WDT_MODE_ENABLE, + MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY); + + return wdt_sta; +} + +void do_hard_reset(void) +{ + write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY); +} |