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Diffstat (limited to 'src/soc/mediatek/common/rtc.c')
-rw-r--r--src/soc/mediatek/common/rtc.c40
1 files changed, 37 insertions, 3 deletions
diff --git a/src/soc/mediatek/common/rtc.c b/src/soc/mediatek/common/rtc.c
index 0925f7f6f8..95bd13b892 100644
--- a/src/soc/mediatek/common/rtc.c
+++ b/src/soc/mediatek/common/rtc.c
@@ -2,7 +2,6 @@
#include <soc/rtc_common.h>
#include <soc/rtc.h>
-#include <soc/pmic_wrap.h>
#include <timer.h>
/* ensure rtc write success */
@@ -94,6 +93,30 @@ int rtc_xosc_write(u16 val)
return rtc_write_trigger();
}
+/* enable lpd subroutine */
+int rtc_lpen(u16 con)
+{
+ con &= ~RTC_CON_LPRST;
+ rtc_write(RTC_CON, con);
+
+ if (!rtc_write_trigger())
+ return 0;
+
+ con |= RTC_CON_LPRST;
+ rtc_write(RTC_CON, con);
+
+ if (!rtc_write_trigger())
+ return 0;
+
+ con &= ~RTC_CON_LPRST;
+ rtc_write(RTC_CON, con);
+
+ if (!rtc_write_trigger())
+ return 0;
+
+ return 1;
+}
+
/* initialize rtc related registers */
int rtc_reg_init(void)
{
@@ -129,6 +152,14 @@ int rtc_reg_init(void)
return rtc_write_trigger();
}
+/* write powerkeys to enable rtc functions */
+int rtc_powerkey_init(void)
+{
+ rtc_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY);
+ rtc_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY);
+ return rtc_write_trigger();
+}
+
static u8 rtc_check_state(void)
{
u16 con;
@@ -164,18 +195,21 @@ void rtc_boot_common(void)
switch (rtc_check_state()) {
case RTC_STATE_REBOOT:
- pwrap_write_field(RTC_BBPU, RTC_BBPU_KEY | RTC_BBPU_RELOAD,
- 0xFFFF, 0);
+ rtc_read(RTC_BBPU, &bbpu);
+ rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
rtc_write_trigger();
rtc_osc_init();
+ rtc_info("RTC_STATE_REBOOT\n");
break;
case RTC_STATE_RECOVER:
rtc_init(1);
+ rtc_info("RTC_STATE_RECOVER\n");
break;
case RTC_STATE_INIT:
default:
if (rtc_init(0))
rtc_init(1);
+ rtc_info("RTC_STATE_INIT\n");
break;
}