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-rw-r--r--src/soc/intel/cannonlake/cpu.c2
-rw-r--r--src/soc/intel/common/block/sgx/sgx.c2
-rw-r--r--src/soc/intel/skylake/cpu.c2
3 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index 26d8c2ea97..89d3493889 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -312,6 +312,6 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
if (msr2.lo && (current_patch_id == new_patch_id - 1))
return 0;
- return (msr1.lo & PRMRR_SUPPORTED) &&
+ return (msr1.lo & MTRR_CAP_PRMRR) &&
(current_patch_id == new_patch_id - 1);
}
diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c
index 5f14909361..56648c81ea 100644
--- a/src/soc/intel/common/block/sgx/sgx.c
+++ b/src/soc/intel/common/block/sgx/sgx.c
@@ -28,7 +28,7 @@ static int is_sgx_supported(void)
cpuid_regs = cpuid_ext(0x7, 0x0); /* EBX[2] is feature capability */
msr = rdmsr(MTRR_CAP_MSR); /* Bit 12 is PRMRR enablement */
- return ((cpuid_regs.ebx & SGX_SUPPORTED) && (msr.lo & PRMRR_SUPPORTED));
+ return ((cpuid_regs.ebx & SGX_SUPPORTED) && (msr.lo & MTRR_CAP_PRMRR));
}
void prmrr_core_configure(void)
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 49d817ffef..a545435599 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -355,6 +355,6 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
if (msr2.lo && (current_patch_id == new_patch_id - 1))
return 0;
else
- return (msr1.lo & PRMRR_SUPPORTED) &&
+ return (msr1.lo & MTRR_CAP_PRMRR) &&
(current_patch_id == new_patch_id - 1);
}