summaryrefslogtreecommitdiff
path: root/src/soc/intel
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/denverton_ns/include/soc/pm.h3
-rw-r--r--src/soc/intel/denverton_ns/pmutil.c12
2 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h
index 2dc40a5e6c..faf7f20506 100644
--- a/src/soc/intel/denverton_ns/include/soc/pm.h
+++ b/src/soc/intel/denverton_ns/include/soc/pm.h
@@ -28,6 +28,9 @@ struct chipset_power_state {
uint32_t prev_sleep_state;
} __attribute__((packed));
+/* Get base address PMC memory mapped registers. */
+uint8_t *pmc_mmio_regs(void);
+
struct chipset_power_state *fill_power_state(void);
/* Power Management Utility Functions. */
diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c
index 822e50e397..b861513def 100644
--- a/src/soc/intel/denverton_ns/pmutil.c
+++ b/src/soc/intel/denverton_ns/pmutil.c
@@ -84,6 +84,18 @@ void enable_smi(uint32_t mask)
outl(smi_en, (uint16_t)(pmbase + SMI_EN));
}
+uint8_t *pmc_mmio_regs(void)
+{
+ uint32_t reg32;
+
+ reg32 = pci_read_config32(PCH_DEV_PMC, PMC_PWRM_BASE);
+
+ /* 4KiB alignment. */
+ reg32 &= ~0xfff;
+
+ return (void *)(uintptr_t) reg32;
+}
+
void disable_smi(uint32_t mask)
{
uint16_t pmbase = get_pmbase();