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-rw-r--r--src/soc/intel/alderlake/Kconfig8
-rw-r--r--src/soc/intel/common/block/usb4/Kconfig8
2 files changed, 10 insertions, 6 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 1e16b42bcb..e2116c787e 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -148,11 +148,7 @@ config HEAP_SIZE
# - 42 buses
# - 194 MiB Non-prefetchable memory
# - 448 MiB Prefetchable memory
-config ADL_ENABLE_USB4_PCIE_RESOURCES
- def_bool n
- select PCIEXP_HOTPLUG
-
-if ADL_ENABLE_USB4_PCIE_RESOURCES
+if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
config PCIEXP_HOTPLUG_BUSES
int
@@ -166,7 +162,7 @@ config PCIEXP_HOTPLUG_PREFETCH_MEM
hex
default 0x1c000000
-endif # ADL_ENABLE_USB4_PCIE_RESOURCES
+endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
config MAX_PCH_ROOT_PORTS
int
diff --git a/src/soc/intel/common/block/usb4/Kconfig b/src/soc/intel/common/block/usb4/Kconfig
index fb876e1fd9..d4e1c25aa1 100644
--- a/src/soc/intel/common/block/usb4/Kconfig
+++ b/src/soc/intel/common/block/usb4/Kconfig
@@ -18,3 +18,11 @@ config SOC_INTEL_COMMON_BLOCK_USB4_XHCI
help
Minimal PCI driver for adding PCI ops and SSDT generation for common
Intel USB4/Thunderbolt North XHCI ports.
+
+config SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+ bool
+ default n
+ depends on SOC_INTEL_COMMON_BLOCK_USB4
+ select PCIEXP_HOTPLUG
+ help
+ Enable USB4 PCIe resources for reserving hotplug busses and memory.