summaryrefslogtreecommitdiff
path: root/src/soc/intel
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/alderlake/bootblock/report_platform.c4
-rw-r--r--src/soc/intel/alderlake/chip.h11
-rw-r--r--src/soc/intel/alderlake/chipset.cb24
-rw-r--r--src/soc/intel/alderlake/cpu.c4
-rw-r--r--src/soc/intel/alderlake/fsp_params.c4
-rw-r--r--src/soc/intel/alderlake/vr_config.c80
-rw-r--r--src/soc/intel/common/block/systemagent/systemagent.c4
7 files changed, 107 insertions, 24 deletions
diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c
index 6372cd6751..57e4f522da 100644
--- a/src/soc/intel/alderlake/bootblock/report_platform.c
+++ b/src/soc/intel/alderlake/bootblock/report_platform.c
@@ -63,6 +63,10 @@ static struct {
{ PCI_DID_INTEL_ADL_N_ID_3, "Alderlake-N" },
{ PCI_DID_INTEL_ADL_N_ID_4, "Alderlake-N" },
{ PCI_DID_INTEL_ADL_N_ID_5, "Alderlake-N" },
+ { PCI_DID_INTEL_ADL_N_ID_6, "Alderlake-N" },
+ { PCI_DID_INTEL_ADL_N_ID_7, "Alderlake-N" },
+ { PCI_DID_INTEL_ADL_N_ID_8, "Alderlake-N" },
+ { PCI_DID_INTEL_ADL_N_ID_9, "Alderlake-N" },
{ PCI_DID_INTEL_ADL_S_ID_1, "Alderlake-S (8+8)" },
{ PCI_DID_INTEL_ADL_S_ID_2, "Alderlake-S" },
{ PCI_DID_INTEL_ADL_S_ID_3, "Alderlake-S (8+4)" },
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index c8005dea2c..67d83b4639 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -54,9 +54,13 @@ enum soc_intel_alderlake_power_limits {
ADL_M_242_CORE,
ADL_P_442_45W_CORE,
ADL_N_081_7W_CORE,
+ ADL_N_081_9W_CORE,
ADL_N_081_15W_CORE,
ADL_N_041_6W_CORE,
+ ADL_N_041_12W_CORE,
+ ADL_N_041_15W_CORE,
ADL_N_021_6W_CORE,
+ ADL_N_021_10W_CORE,
ADL_S_882_35W_CORE,
ADL_S_882_65W_CORE,
ADL_S_882_125W_CORE,
@@ -111,6 +115,7 @@ enum soc_intel_alderlake_cpu_tdps {
TDP_6W = 6,
TDP_7W = 7,
TDP_9W = 9,
+ TDP_10W = 10,
TDP_12W = 12,
TDP_15W = 15,
TDP_28W = 28,
@@ -148,12 +153,16 @@ static const struct {
{ PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W },
{ PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W },
{ PCI_DID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W },
- { PCI_DID_INTEL_ADL_N_ID_1, ADL_N_081_7W_CORE, TDP_7W },
{ PCI_DID_INTEL_ADL_N_ID_1, ADL_N_081_15W_CORE, TDP_15W },
{ PCI_DID_INTEL_ADL_N_ID_2, ADL_N_041_6W_CORE, TDP_6W },
{ PCI_DID_INTEL_ADL_N_ID_3, ADL_N_041_6W_CORE, TDP_6W },
{ PCI_DID_INTEL_ADL_N_ID_4, ADL_N_021_6W_CORE, TDP_6W },
{ PCI_DID_INTEL_ADL_N_ID_5, ADL_N_041_6W_CORE, TDP_6W },
+ { PCI_DID_INTEL_ADL_N_ID_5, ADL_N_041_15W_CORE, TDP_15W },
+ { PCI_DID_INTEL_ADL_N_ID_6, ADL_N_041_12W_CORE, TDP_12W },
+ { PCI_DID_INTEL_ADL_N_ID_7, ADL_N_041_12W_CORE, TDP_12W },
+ { PCI_DID_INTEL_ADL_N_ID_8, ADL_N_021_6W_CORE, TDP_6W },
+ { PCI_DID_INTEL_ADL_N_ID_9, ADL_N_021_10W_CORE, TDP_10W },
{ PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_35W_CORE, TDP_35W },
{ PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_65W_CORE, TDP_65W },
{ PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_125W_CORE, TDP_125W },
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb
index 0ab7c8a87a..7ae1990eda 100644
--- a/src/soc/intel/alderlake/chipset.cb
+++ b/src/soc/intel/alderlake/chipset.cb
@@ -54,6 +54,12 @@ chip soc/intel/alderlake
.tdp_pl4 = 78,
}"
+ register "power_limits_config[ADL_N_081_9W_CORE]" = "{
+ .tdp_pl1_override = 9,
+ .tdp_pl2_override = 35,
+ .tdp_pl4 = 83,
+ }"
+
register "power_limits_config[ADL_N_081_15W_CORE]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 35,
@@ -66,12 +72,30 @@ chip soc/intel/alderlake
.tdp_pl4 = 78,
}"
+ register "power_limits_config[ADL_N_041_12W_CORE]" = "{
+ .tdp_pl1_override = 12,
+ .tdp_pl2_override = 25,
+ .tdp_pl4 = 78,
+ }"
+
+ register "power_limits_config[ADL_N_041_15W_CORE]" = "{
+ .tdp_pl1_override = 15,
+ .tdp_pl2_override = 35,
+ .tdp_pl4 = 83,
+ }"
+
register "power_limits_config[ADL_N_021_6W_CORE]" = "{
.tdp_pl1_override = 6,
.tdp_pl2_override = 25,
.tdp_pl4 = 78,
}"
+ register "power_limits_config[ADL_N_021_10W_CORE]" = "{
+ .tdp_pl1_override = 10,
+ .tdp_pl2_override = 25,
+ .tdp_pl4 = 78,
+ }"
+
register "power_limits_config[RPL_P_682_642_482_45W_CORE]" = "{
.tdp_pl1_override = 45,
.tdp_pl2_override = 115,
diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c
index 92b253216a..255082f1f8 100644
--- a/src/soc/intel/alderlake/cpu.c
+++ b/src/soc/intel/alderlake/cpu.c
@@ -242,6 +242,10 @@ enum adl_cpu_type get_adl_cpu_type(void)
PCI_DID_INTEL_ADL_N_ID_3,
PCI_DID_INTEL_ADL_N_ID_4,
PCI_DID_INTEL_ADL_N_ID_5,
+ PCI_DID_INTEL_ADL_N_ID_6,
+ PCI_DID_INTEL_ADL_N_ID_7,
+ PCI_DID_INTEL_ADL_N_ID_8,
+ PCI_DID_INTEL_ADL_N_ID_9,
};
const uint16_t rpl_hx_mch_ids[] = {
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 8dca5b081c..8c4c29122d 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -596,6 +596,10 @@ static uint16_t get_vccin_aux_imon_iccmax(const struct soc_intel_alderlake_confi
case PCI_DID_INTEL_ADL_N_ID_3:
case PCI_DID_INTEL_ADL_N_ID_4:
case PCI_DID_INTEL_ADL_N_ID_5:
+ case PCI_DID_INTEL_ADL_N_ID_6:
+ case PCI_DID_INTEL_ADL_N_ID_7:
+ case PCI_DID_INTEL_ADL_N_ID_8:
+ case PCI_DID_INTEL_ADL_N_ID_9:
return config->vccin_aux_imon_iccmax
? config->vccin_aux_imon_iccmax : ICC_MAX_ID_ADL_N_MA;
case PCI_DID_INTEL_ADL_S_ID_1:
diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c
index c3584ba01f..95dba9fbd0 100644
--- a/src/soc/intel/alderlake/vr_config.c
+++ b/src/soc/intel/alderlake/vr_config.c
@@ -123,11 +123,17 @@ static const struct vr_lookup vr_config_ll[] = {
{ PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
{ PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
{ PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_LOADLINE(4.7, 6.5) },
- { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
- { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
- { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
- { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
- { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
+ { PCI_DID_INTEL_ADL_N_ID_1, 9, VR_CFG_ALL_DOMAINS_LOADLINE(4.7, 6.5) },
+ { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
+ { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
+ { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
+ { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
+ { PCI_DID_INTEL_ADL_N_ID_5, 15, VR_CFG_ALL_DOMAINS_LOADLINE(4.7, 6.5) },
+ { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
+ { PCI_DID_INTEL_ADL_N_ID_6, 12, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
+ { PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
+ { PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
+ { PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) },
{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
{ PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
@@ -187,11 +193,17 @@ static const struct vr_lookup vr_config_icc[] = {
{ PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
{ PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
{ PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_ICC(53, 29) },
- { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_ICC(37, 29) },
- { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_ICC(37, 29) },
- { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_ICC(37, 26) },
- { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_ICC(27, 23) },
- { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_ICC(37, 29) },
+ { PCI_DID_INTEL_ADL_N_ID_1, 9, VR_CFG_ALL_DOMAINS_ICC(53, 29) },
+ { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_ICC(37, 29) },
+ { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_ICC(37, 29) },
+ { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_ICC(37, 26) },
+ { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_ICC(27, 23) },
+ { PCI_DID_INTEL_ADL_N_ID_5, 15, VR_CFG_ALL_DOMAINS_ICC(53, 29) },
+ { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_ICC(37, 29) },
+ { PCI_DID_INTEL_ADL_N_ID_6, 12, VR_CFG_ALL_DOMAINS_ICC(37, 29) },
+ { PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_ICC(37, 23) },
+ { PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_ICC(27, 23) },
+ { PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_ICC(27, 23) },
{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) },
{ PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
@@ -251,11 +263,17 @@ static const struct vr_lookup vr_config_tdc_timewindow[] = {
{ PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
- { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
- { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
- { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
- { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
- { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+ { PCI_DID_INTEL_ADL_N_ID_1, 9, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+ { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+ { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+ { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+ { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+ { PCI_DID_INTEL_ADL_N_ID_5, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+ { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+ { PCI_DID_INTEL_ADL_N_ID_6, 12, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+ { PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+ { PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+ { PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
{ PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
@@ -314,12 +332,18 @@ static const struct vr_lookup vr_config_tdc_currentlimit[] = {
{ PCI_DID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) },
{ PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) },
{ PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) },
- { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) },
- { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_TDC_CURRENT(14, 14) },
- { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) },
- { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) },
- { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(10, 10) },
- { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) },
+ { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 20) },
+ { PCI_DID_INTEL_ADL_N_ID_1, 9, VR_CFG_ALL_DOMAINS_TDC_CURRENT(17, 16) },
+ { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_TDC_CURRENT(14, 14) },
+ { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 20) },
+ { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 20) },
+ { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 16) },
+ { PCI_DID_INTEL_ADL_N_ID_5, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 20) },
+ { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 20) },
+ { PCI_DID_INTEL_ADL_N_ID_6, 12, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 20) },
+ { PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 20) },
+ { PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 16) },
+ { PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 16) },
{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) },
{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(33, 33) },
{ PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) },
@@ -404,8 +428,10 @@ void fill_vr_domain_config(FSP_S_CONFIG *s_cfg,
s_cfg->TdcCurrentLimit[domain] = cfg->tdc_currentlimit;
} else {
uint8_t tdp = get_cpu_tdp();
- struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
- uint16_t mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
+ struct device *sa = pcidev_path_on_root(SA_DEVFN_ROOT);
+ struct device *gt = pcidev_path_on_root(SA_DEVFN_IGD);
+ uint16_t mch_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xffff;
+ uint16_t gt_id = gt ? pci_read_config16(gt, PCI_DEVICE_ID) : 0xffff;
s_cfg->AcLoadline[domain] = load_table(vr_config_ll, ARRAY_SIZE(vr_config_ll),
domain, mch_id, tdp);
@@ -419,6 +445,14 @@ void fill_vr_domain_config(FSP_S_CONFIG *s_cfg,
s_cfg->TdcCurrentLimit[domain] = load_table(vr_config_tdc_currentlimit,
ARRAY_SIZE(vr_config_tdc_currentlimit),
domain, mch_id, tdp);
+
+ /* Exception: following ADL-N SKUs may have different GT TDC based on GT ID */
+ if (mch_id == PCI_DID_INTEL_ADL_N_ID_2 || mch_id == PCI_DID_INTEL_ADL_N_ID_3) {
+ if (gt_id == PCI_DID_INTEL_ADL_N_GT1)
+ s_cfg->TdcCurrentLimit[VR_DOMAIN_GT] = VR_CFG_AMP(20);
+ else if (gt_id == PCI_DID_INTEL_ADL_N_GT2)
+ s_cfg->TdcCurrentLimit[VR_DOMAIN_GT] = VR_CFG_AMP(19);
+ }
}
fill_vr_fast_vmode(s_cfg, domain, chip_cfg);
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index 6239a46a8e..3b7163367f 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -531,6 +531,10 @@ static const unsigned short systemagent_ids[] = {
PCI_DID_INTEL_ADL_N_ID_3,
PCI_DID_INTEL_ADL_N_ID_4,
PCI_DID_INTEL_ADL_N_ID_5,
+ PCI_DID_INTEL_ADL_N_ID_6,
+ PCI_DID_INTEL_ADL_N_ID_7,
+ PCI_DID_INTEL_ADL_N_ID_8,
+ PCI_DID_INTEL_ADL_N_ID_9,
PCI_DID_INTEL_RPL_HX_ID_1,
PCI_DID_INTEL_RPL_HX_ID_2,
PCI_DID_INTEL_RPL_HX_ID_3,
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 16:51:39 +0000