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-rw-r--r--src/soc/intel/xeon_sp/config.c5
-rw-r--r--src/soc/intel/xeon_sp/gnr/romstage.c15
-rw-r--r--src/soc/intel/xeon_sp/include/soc/config.h8
3 files changed, 28 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/config.c b/src/soc/intel/xeon_sp/config.c
index c2a908c984..a61f724ae1 100644
--- a/src/soc/intel/xeon_sp/config.c
+++ b/src/soc/intel/xeon_sp/config.c
@@ -6,3 +6,8 @@ __weak enum xeonsp_cxl_mode get_cxl_mode(void)
{
return XEONSP_CXL_DISABLED;
}
+
+__weak enum xeonsp_fast_boot_mode get_fast_boot_mode(void)
+{
+ return XEONSP_FAST_BOOT_COLD | XEONSP_FAST_BOOT_WARM;
+}
diff --git a/src/soc/intel/xeon_sp/gnr/romstage.c b/src/soc/intel/xeon_sp/gnr/romstage.c
index 95b2e15a5d..0c3aed0419 100644
--- a/src/soc/intel/xeon_sp/gnr/romstage.c
+++ b/src/soc/intel/xeon_sp/gnr/romstage.c
@@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <console/console.h>
+#include <soc/config.h>
#include <soc/romstage.h>
static uint8_t get_mmcfg_base_upd_index(const uint64_t base_addr)
@@ -48,6 +50,19 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
m_cfg->mmCfgBase = get_mmcfg_base_upd_index(CONFIG_ECAM_MMCONF_BASE_ADDRESS);
m_cfg->mmCfgSize = get_mmcfg_size_upd_index(CONFIG_ECAM_MMCONF_LENGTH);
+ /* fast boot setting */
+ int fast_boot_mode = get_fast_boot_mode();
+ m_cfg->AttemptFastBoot = !!(fast_boot_mode & XEONSP_FAST_BOOT_WARM);
+ m_cfg->AttemptFastBootCold = !!(fast_boot_mode & XEONSP_FAST_BOOT_COLD);
+
+ FSPM_ARCH2_UPD *arch_upd = &mupd->FspmArchUpd;
+ if (fast_boot_mode == XEONSP_FAST_BOOT_DISABLED) {
+ arch_upd->BootMode =
+ FSP_BOOT_WITH_FULL_CONFIGURATION;
+ printk(BIOS_NOTICE, "Reset BootMode as "
+ "FSP_BOOT_WITH_FULL_CONFIGURATION.\n");
+ }
+
/* Board level settings */
mainboard_memory_init_params(mupd);
}
diff --git a/src/soc/intel/xeon_sp/include/soc/config.h b/src/soc/intel/xeon_sp/include/soc/config.h
index 6d5f3d587d..66538f5a28 100644
--- a/src/soc/intel/xeon_sp/include/soc/config.h
+++ b/src/soc/intel/xeon_sp/include/soc/config.h
@@ -11,4 +11,12 @@ enum xeonsp_cxl_mode {
enum xeonsp_cxl_mode get_cxl_mode(void);
+enum xeonsp_fast_boot_mode {
+ XEONSP_FAST_BOOT_DISABLED = 0x0,
+ XEONSP_FAST_BOOT_COLD = 0x1,
+ XEONSP_FAST_BOOT_WARM = 0x2,
+};
+
+enum xeonsp_fast_boot_mode get_fast_boot_mode(void);
+
#endif