diff options
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/apollolake/Kconfig | 18 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/Makefile.inc | 8 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/acpi/pci_irqs.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/acpi/xhci.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/bootblock/bootblock.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 14 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/cpu.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/gpio.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/pcr_ids.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/pm.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/lpc.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/meminit.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/romstage.c | 8 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/uart.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/xhci.c | 2 |
15 files changed, 35 insertions, 35 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 96808cf1a1..fec0fc94cf 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -3,7 +3,7 @@ config SOC_INTEL_APOLLOLAKE help Intel Apollolake support -config SOC_INTEL_GLK +config SOC_INTEL_GEMINILAKE bool default n select SOC_INTEL_APOLLOLAKE @@ -44,7 +44,7 @@ config CPU_SPECIFIC_OPTIONS select GENERIC_GPIO_LIB select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER - select HAVE_INTEL_FSP_REPO if !SOC_INTEL_GLK + select HAVE_INTEL_FSP_REPO if !SOC_INTEL_GEMINILAKE select MRC_SETTINGS_PROTECT select MRC_SETTINGS_VARIABLE_DATA select NO_XIP_EARLY_STAGES @@ -96,8 +96,8 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select TSC_MONOTONIC_TIMER select PLATFORM_USES_FSP2_0 - select UDK_2015_BINDING if !SOC_INTEL_GLK - select UDK_2017_BINDING if SOC_INTEL_GLK + select UDK_2015_BINDING if !SOC_INTEL_GEMINILAKE + select UDK_2017_BINDING if SOC_INTEL_GEMINILAKE select SOC_INTEL_COMMON_RESET select HAVE_CF9_RESET_PREPARE select INTEL_GMA_ADD_VBT if RUN_FSP_GOP @@ -138,7 +138,7 @@ config DCACHE_RAM_BASE config DCACHE_RAM_SIZE hex - default 0x100000 if SOC_INTEL_GLK + default 0x100000 if SOC_INTEL_GEMINILAKE default 0xc0000 help The size of the cache-as-ram region required during bootblock @@ -183,7 +183,7 @@ config VERSTAGE_ADDR The base address (in CAR) where verstage should be linked config FSP_HEADER_PATH - default "src/vendorcode/intel/fsp/fsp2_0/glk" if SOC_INTEL_GLK + default "src/vendorcode/intel/fsp/fsp2_0/glk" if SOC_INTEL_GEMINILAKE default "3rdparty/fsp/ApolloLakeFspBinPkg/Include/" config FSP_FD_PATH @@ -293,7 +293,7 @@ config NHLT_RT5682 choice prompt "Cache-as-ram implementation" - default CAR_CQOS if !SOC_INTEL_GLK + default CAR_CQOS if !SOC_INTEL_GEMINILAKE default CAR_NEM help This option allows you to select how cache-as-ram (CAR) is set up. @@ -335,7 +335,7 @@ config CACHE_QOS_SIZE_PER_BIT config L2_CACHE_SIZE hex - default 0x400000 if SOC_INTEL_GLK + default 0x400000 if SOC_INTEL_GEMINILAKE default 0x100000 config SMM_RESERVED_SIZE @@ -344,7 +344,7 @@ config SMM_RESERVED_SIZE config IFD_CHIPSET string - default "glk" if SOC_INTEL_GLK + default "glk" if SOC_INTEL_GEMINILAKE default "aplk" config CPU_BCLK_MHZ diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index a20a554be1..79fab1a9d1 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -30,7 +30,7 @@ romstage-y += heci.c romstage-y += i2c.c romstage-y += uart.c romstage-y += meminit.c -ifeq ($(CONFIG_SOC_INTEL_GLK),y) +ifeq ($(CONFIG_SOC_INTEL_GEMINILAKE),y) romstage-y += meminit_util_glk.c else romstage-y += meminit_util_apl.c @@ -90,7 +90,7 @@ verstage-y += pmutil.c verstage-y += reset.c verstage-y += spi.c -ifeq ($(CONFIG_SOC_INTEL_GLK),y) +ifeq ($(CONFIG_SOC_INTEL_GEMINILAKE),y) bootblock-y += gpio_glk.c romstage-y += gpio_glk.c smm-y += gpio_glk.c @@ -149,7 +149,7 @@ files_added:: $(IFWITOOL) endif # DSP firmware settings files. -ifeq ($(CONFIG_SOC_INTEL_GLK),y) +ifeq ($(CONFIG_SOC_INTEL_GEMINILAKE),y) NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/glk/nhlt-blobs else NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/apollolake/nhlt-blobs @@ -185,7 +185,7 @@ cbfs-files-$(CONFIG_NHLT_RT5682) += $(RT5682_RENDER_CAPTURE) $(RT5682_RENDER_CAPTURE)-file := $(NHLT_BLOB_PATH)/$(RT5682_RENDER_CAPTURE) $(RT5682_RENDER_CAPTURE)-type := raw -ifeq ($(CONFIG_SOC_INTEL_GLK),y) +ifeq ($(CONFIG_SOC_INTEL_GEMINILAKE),y) # Gemini Lake B0 (706a1) only atm. cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-7a-*) else diff --git a/src/soc/intel/apollolake/acpi/pci_irqs.asl b/src/soc/intel/apollolake/acpi/pci_irqs.asl index d9c180d0f5..7c5b83052b 100644 --- a/src/soc/intel/apollolake/acpi/pci_irqs.asl +++ b/src/soc/intel/apollolake/acpi/pci_irqs.asl @@ -15,7 +15,7 @@ Method(_PRT) Package(){0x000FFFFF, 0, 0, CSE_INT}, Package(){0x0011FFFF, 0, 0, ISH_INT}, Package(){0x0012FFFF, 0, 0, SATA_INT}, -#if CONFIG(SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GEMINILAKE) Package(){0x000CFFFF, 0, 0, CNVI_INT}, Package(){0x0013FFFF, 0, 0, PIRQF_INT}, Package(){0x0013FFFF, 1, 0, PIRQF_INT}, diff --git a/src/soc/intel/apollolake/acpi/xhci.asl b/src/soc/intel/apollolake/acpi/xhci.asl index 1b75cdb7b6..1e506225a5 100644 --- a/src/soc/intel/apollolake/acpi/xhci.asl +++ b/src/soc/intel/apollolake/acpi/xhci.asl @@ -21,7 +21,7 @@ Device (XHCI) { /* Root Hub */ Name (_ADR, Zero) -#if CONFIG(SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GEMINILAKE) #include "xhci_glk_ports.asl" #else #include "xhci_apl_ports.asl" diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 2137e4901e..14e9b11ad2 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -23,7 +23,7 @@ #include <spi-generic.h> static const struct pad_config tpm_spi_configs[] = { -#if CONFIG(SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GEMINILAKE) PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ #else PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 22791d9aa5..9f73727b65 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -113,7 +113,7 @@ const char *soc_acpi_name(const struct device *dev) case 6: return "HS07"; case 7: return "HS08"; case 8: - if (CONFIG(SOC_INTEL_GLK)) + if (CONFIG(SOC_INTEL_GEMINILAKE)) return "HS09"; } break; @@ -445,7 +445,7 @@ static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig) case PCH_DEVFN_SMBUS: silconfig->SmbusEnable = 0; break; -#if !CONFIG(SOC_INTEL_GLK) +#if !CONFIG(SOC_INTEL_GEMINILAKE) case SA_DEVFN_IPU: silconfig->IpuEn = 0; break; @@ -479,7 +479,7 @@ static void parse_devicetree(FSP_S_CONFIG *silconfig) static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig) { -#if !CONFIG(SOC_INTEL_GLK) /* GLK FSP does not have these fields in FspsUpd.h yet */ +#if !CONFIG(SOC_INTEL_GEMINILAKE) /* GLK FSP does not have these fields in FspsUpd.h yet */ uint8_t port; for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) { @@ -535,7 +535,7 @@ static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config static void glk_fsp_silicon_init_params_cb( struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig) { -#if CONFIG(SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GEMINILAKE) uint8_t port; struct device *dev; @@ -665,7 +665,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) /* Disable monitor mwait since it is broken due to a hardware bug * without a fix. Specific to Apollolake. */ - if (!CONFIG(SOC_INTEL_GLK)) + if (!CONFIG(SOC_INTEL_GEMINILAKE)) silconfig->MonitorMwaitEnable = 0; silconfig->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT); @@ -681,7 +681,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; /* BIOS config lockdown Audio clk and power gate */ silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown; - if (CONFIG(SOC_INTEL_GLK)) + if (CONFIG(SOC_INTEL_GEMINILAKE)) glk_fsp_silicon_init_params_cb(cfg, silconfig); else apl_fsp_silicon_init_params_cb(cfg, silconfig); @@ -813,7 +813,7 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase) * Override GLK xhci clock gating register(XHCLKGTEN) to * mitigate USB device suspend and resume failure. */ - if (CONFIG(SOC_INTEL_GLK)) { + if (CONFIG(SOC_INTEL_GEMINILAKE)) { uint32_t *cfg; const struct resource *res; uint32_t reg; diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index eb07e1e104..72f983f3dd 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -30,7 +30,7 @@ #include <soc/pm.h> static const struct reg_script core_msr_script[] = { -#if !CONFIG(SOC_INTEL_GLK) +#if !CONFIG(SOC_INTEL_GEMINILAKE) /* Enable C-state and IO/MWAIT redirect */ REG_MSR_WRITE(MSR_PKG_CST_CONFIG_CONTROL, (PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h index b672f242bd..9b809c000a 100644 --- a/src/soc/intel/apollolake/include/soc/gpio.h +++ b/src/soc/intel/apollolake/include/soc/gpio.h @@ -3,7 +3,7 @@ #ifndef _SOC_APL_GPIO_H_ #define _SOC_APL_GPIO_H_ -#if CONFIG(SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GEMINILAKE) #include <soc/gpio_glk.h> #else #include <soc/gpio_apl.h> diff --git a/src/soc/intel/apollolake/include/soc/pcr_ids.h b/src/soc/intel/apollolake/include/soc/pcr_ids.h index 96466f0f6d..4e043bbb95 100644 --- a/src/soc/intel/apollolake/include/soc/pcr_ids.h +++ b/src/soc/intel/apollolake/include/soc/pcr_ids.h @@ -6,7 +6,7 @@ /* * Port ids. */ -#if CONFIG(SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GEMINILAKE) #define PID_GPIO_AUDIO 0xC9 #define PID_GPIO_SCC 0xC8 #else diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index eb8c077874..aaf62583e6 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -177,7 +177,7 @@ #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4 + 4*(x)) -#if CONFIG(SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GEMINILAKE) #define PMC_GPE_AUDIO_31_0 9 #define PMC_GPE_N_95_64 8 #define PMC_GPE_N_63_32 7 diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index be6777ff7f..ad9211b9c2 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -28,7 +28,7 @@ const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void) } static const struct pad_config lpc_gpios[] = { -#if CONFIG(SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GEMINILAKE) #if !CONFIG(SOC_ESPI) PAD_CFG_NF(GPIO_147, UP_20K, DEEP, NF1), /* LPC_ILB_SERIRQ */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_148, NONE, DEEP, NF1, HIZCRx1, diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index e391a92345..86015715bc 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -152,7 +152,7 @@ static const struct fsp_speed_profiles glk_profile = { static const struct fsp_speed_profiles *get_fsp_profile(void) { - if (CONFIG(SOC_INTEL_GLK)) + if (CONFIG(SOC_INTEL_GEMINILAKE)) return &glk_profile; else return &apl_profile; diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 48ae9a726d..141fae003a 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -107,7 +107,7 @@ static bool punit_init(void) PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER | PUINT_THERMAL_DEVICE_IRQ_LOCK; - if (!CONFIG(SOC_INTEL_GLK)) { + if (!CONFIG(SOC_INTEL_GEMINILAKE)) { data = MCHBAR32(0x7818); data &= 0xFFFFE01F; data |= 0x20 | 0x200; @@ -231,7 +231,7 @@ static void check_full_retrain(const FSPM_UPD *mupd) static void soc_memory_init_params(FSPM_UPD *mupd) { -#if CONFIG(SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GEMINILAKE) /* Only for GLK */ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; @@ -258,7 +258,7 @@ static void parse_devicetree_setting(FSPM_UPD *m_upd) { DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_NPK); -#if CONFIG(SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GEMINILAKE) m_upd->FspmConfig.TraceHubEn = is_dev_enabled(dev); #else m_upd->FspmConfig.NpkEn = is_dev_enabled(dev); @@ -271,7 +271,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) fill_console_params(mupd); - if (CONFIG(SOC_INTEL_GLK)) + if (CONFIG(SOC_INTEL_GEMINILAKE)) soc_memory_init_params(mupd); mainboard_memory_init_params(mupd); diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index 038279ec81..4e35ee5a0a 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -13,7 +13,7 @@ /* UART pad configuration. Support RXD and TXD for now. */ const struct uart_gpio_pad_config uart_gpio_pads[] = { -#if CONFIG(SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GEMINILAKE) { .console_index = 0, .gpios = { diff --git a/src/soc/intel/apollolake/xhci.c b/src/soc/intel/apollolake/xhci.c index 4396eaa67d..4584dc7085 100644 --- a/src/soc/intel/apollolake/xhci.c +++ b/src/soc/intel/apollolake/xhci.c @@ -3,7 +3,7 @@ #include <intelblocks/xhci.h> #define XHCI_USB2_PORT_STATUS_REG 0x480 -#if CONFIG(SOC_INTEL_GLK) +#if CONFIG(SOC_INTEL_GEMINILAKE) #define XHCI_USB3_PORT_STATUS_REG 0x510 #define XHCI_USB2_PORT_NUM 9 #else |