diff options
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/elkhartlake/chip.c | 18 | ||||
| -rw-r--r-- | src/soc/intel/elkhartlake/include/soc/pci_devs.h | 146 |
2 files changed, 67 insertions, 97 deletions
diff --git a/src/soc/intel/elkhartlake/chip.c b/src/soc/intel/elkhartlake/chip.c index cd65260c10..8b4cf0cad9 100644 --- a/src/soc/intel/elkhartlake/chip.c +++ b/src/soc/intel/elkhartlake/chip.c @@ -17,7 +17,7 @@ #include <soc/soc_chip.h> static const struct pcie_rp_group pch_rp_groups[] = { - { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE, .count = 7 }, { 0 } }; @@ -64,16 +64,17 @@ const char *soc_acpi_name(const struct device *dev) switch (dev->path.pci.devfn) { case SA_DEVFN_ROOT: return "MCHC"; - case SA_DEVFN_IPU: return "IPU0"; - case PCH_DEVFN_ISH: return "ISHB"; + case PCH_DEVFN_I2C6: return "I2C6"; + case PCH_DEVFN_I2C7: return "I2C7"; case PCH_DEVFN_XHCI: return "XHCI"; case PCH_DEVFN_I2C0: return "I2C0"; case PCH_DEVFN_I2C1: return "I2C1"; case PCH_DEVFN_I2C2: return "I2C2"; case PCH_DEVFN_I2C3: return "I2C3"; + case PCH_DEVFN_SATA: return "SATA"; + case PCH_DEVFN_UART2: return "UAR2"; case PCH_DEVFN_I2C4: return "I2C4"; case PCH_DEVFN_I2C5: return "I2C5"; - case PCH_DEVFN_SATA: return "SATA"; case PCH_DEVFN_PCIE1: return "RP01"; case PCH_DEVFN_PCIE2: return "RP02"; case PCH_DEVFN_PCIE3: return "RP03"; @@ -81,23 +82,16 @@ const char *soc_acpi_name(const struct device *dev) case PCH_DEVFN_PCIE5: return "RP05"; case PCH_DEVFN_PCIE6: return "RP06"; case PCH_DEVFN_PCIE7: return "RP07"; - case PCH_DEVFN_PCIE8: return "RP08"; - case PCH_DEVFN_PCIE9: return "RP09"; - case PCH_DEVFN_PCIE10: return "RP10"; - case PCH_DEVFN_PCIE11: return "RP11"; - case PCH_DEVFN_PCIE12: return "RP12"; case PCH_DEVFN_UART0: return "UAR0"; case PCH_DEVFN_UART1: return "UAR1"; - case PCH_DEVFN_UART2: return "UAR2"; case PCH_DEVFN_GSPI0: return "SPI0"; case PCH_DEVFN_GSPI1: return "SPI1"; + case PCH_DEVFN_GBE: return "GLAN"; case PCH_DEVFN_GSPI2: return "SPI2"; - case PCH_DEVFN_GSPI3: return "SPI3"; case PCH_DEVFN_EMMC: return "EMMC"; case PCH_DEVFN_SDCARD: return "SDXC"; case PCH_DEVFN_HDA: return "HDAS"; case PCH_DEVFN_SMBUS: return "SBUS"; - case PCH_DEVFN_GBE: return "GLAN"; } return NULL; diff --git a/src/soc/intel/elkhartlake/include/soc/pci_devs.h b/src/soc/intel/elkhartlake/include/soc/pci_devs.h index 0ae7db80bf..659de21ebd 100644 --- a/src/soc/intel/elkhartlake/include/soc/pci_devs.h +++ b/src/soc/intel/elkhartlake/include/soc/pci_devs.h @@ -30,76 +30,58 @@ #define SA_DEVFN_DPTF PCI_DEVFN(SA_DEV_SLOT_DPTF, 0) #define SA_DEV_DPTF PCI_DEV(0, SA_DEV_SLOT_DPTF, 0) -#define SA_DEV_SLOT_TBT 0x07 -#define SA_DEVFN_TBT0 PCI_DEVFN(SA_DEV_SLOT_TBT, 0) -#define SA_DEVFN_TBT1 PCI_DEVFN(SA_DEV_SLOT_TBT, 1) -#define SA_DEVFN_TBT2 PCI_DEVFN(SA_DEV_SLOT_TBT, 2) -#define SA_DEVFN_TBT3 PCI_DEVFN(SA_DEV_SLOT_TBT, 3) -#define SA_DEV_TBT0 PCI_DEV(0, SA_DEV_SLOT_TBT, 0) -#define SA_DEV_TBT1 PCI_DEV(0, SA_DEV_SLOT_TBT, 1) -#define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2) -#define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3) - -#define SA_DEV_SLOT_IPU 0x05 -#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) -#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) +#define SA_DEV_SLOT_GNA 0x08 +#define SA_DEVFN_GNA PCI_DEVFN(SA_DEV_SLOT_GNA, 0) +#define SA_DEV_GNA PCI_DEV(0, SA_DEV_SLOT_GNA, 0) + +#define SA_DEV_SLOT_TRACEHUB 0x09 +#define SA_DEVFN_TRACEHUB PCI_DEVFN(SA_DEV_SLOT_TRACEHUB, 0) +#define SA_DEV_TRACEHUB PCI_DEV(0, SA_DEV_SLOT_TRACEHUB, 0) /* PCH Devices */ -#define PCH_DEV_SLOT_SIO0 0x10 -#define PCH_DEVFN_CNVI_BT _PCH_DEVFN(SIO0, 2) -#define PCH_DEVFN_THC0 _PCH_DEVFN(SIO0, 6) -#define PCH_DEVFN_THC1 _PCH_DEVFN(SIO0, 7) -#define PCH_DEV_CNVI_BT _PCH_DEV(SIO0, 2) -#define PCH_DEV_THC0 _PCH_DEV(SIO0, 6) -#define PCH_DEV_THC1 _PCH_DEV(SIO0, 7) - -#define PCH_DEV_SLOT_SIO1 0x11 -#define PCH_DEVFN_UART3 _PCH_DEVFN(SIO1, 0) -#define PCH_DEV_UART3 _PCH_DEV(SIO1, 0) - -#define PCH_DEV_SLOT_ISH 0x12 -#define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0) -#define PCH_DEVFN_GSPI2 _PCH_DEVFN(ISH, 6) -#define PCH_DEV_ISH _PCH_DEV(ISH, 0) -#define PCH_DEV_GSPI2 _PCH_DEV(ISH, 6) - -#define PCH_DEV_SLOT_SIO2 0x13 -#define PCH_DEVFN_GSPI3 _PCH_DEVFN(SIO2, 0) -#define PCH_DEV_GSPI3 _PCH_DEV(SIO2, 0) +#define PCH_DEV_SLOT_IEH 0x10 +#define PCH_DEVFN_I2C6 _PCH_DEVFN(IEH, 0) +#define PCH_DEVFN_I2C7 _PCH_DEVFN(IEH, 1) +#define PCH_DEVFN_IEH _PCH_DEVFN(IEH, 5) +#define PCH_DEV_I2C6 _PCH_DEV(IEH, 0) +#define PCH_DEV_I2C7 _PCH_DEV(IEH, 1) +#define PCH_DEV_IEH _PCH_DEV(IEH, 5) + +#define PCH_DEV_SLOT_SIO0 0x12 +#define PCH_DEVFN_GSPI2 _PCH_DEVFN(SIO0, 0) +#define PCH_DEVFN_CSE_UMA _PCH_DEVFN(SIO0, 3) +#define PCH_DEVFN_CSE_DMA _PCH_DEVFN(SIO0, 4) +#define PCH_DEVFN_UFS0 _PCH_DEVFN(SIO0, 5) +#define PCH_DEVFN_UFS1 _PCH_DEVFN(SIO0, 7) +#define PCH_DEV_GSPI2 _PCH_DEV(SIO0, 0) +#define PCH_DEV_CSE_UMA _PCH_DEV(SIO0, 3) +#define PCH_DEV_CSE_DMA _PCH_DEV(SIO0, 4) +#define PCH_DEV_UFS0 _PCH_DEV(SIO0, 5) +#define PCH_DEV_UFS1 _PCH_DEV(SIO0, 7) #define PCH_DEV_SLOT_XHCI 0x14 #define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) #define PCH_DEVFN_USBOTG _PCH_DEVFN(XHCI, 1) -#define PCH_DEVFN_SRAM _PCH_DEVFN(XHCI, 2) -#define PCH_DEVFN_CNVI_WIFI _PCH_DEVFN(XHCI, 3) #define PCH_DEV_XHCI _PCH_DEV(XHCI, 0) #define PCH_DEV_USBOTG _PCH_DEV(XHCI, 1) -#define PCH_DEV_SRAM _PCH_DEV(XHCI, 2) -#define PCH_DEV_CNVI_WIFI _PCH_DEV(XHCI, 3) -#define PCH_DEVFN_SDCARD _PCH_DEVFN(XHCI, 5) -#define PCH_DEV_SDCARD _PCH_DEV(XHCI, 5) - -#define PCH_DEV_SLOT_SIO3 0x15 -#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO3, 0) -#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO3, 1) -#define PCH_DEVFN_I2C2 _PCH_DEVFN(SIO3, 2) -#define PCH_DEVFN_I2C3 _PCH_DEVFN(SIO3, 3) -#define PCH_DEV_I2C0 _PCH_DEV(SIO3, 0) -#define PCH_DEV_I2C1 _PCH_DEV(SIO3, 1) -#define PCH_DEV_I2C2 _PCH_DEV(SIO3, 2) -#define PCH_DEV_I2C3 _PCH_DEV(SIO3, 3) + +#define PCH_DEV_SLOT_SIO1 0x15 +#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO1, 0) +#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO1, 1) +#define PCH_DEVFN_I2C2 _PCH_DEVFN(SIO1, 2) +#define PCH_DEVFN_I2C3 _PCH_DEVFN(SIO1, 3) +#define PCH_DEV_I2C0 _PCH_DEV(SIO1, 0) +#define PCH_DEV_I2C1 _PCH_DEV(SIO1, 1) +#define PCH_DEV_I2C2 _PCH_DEV(SIO1, 2) +#define PCH_DEV_I2C3 _PCH_DEV(SIO1, 3) #define PCH_DEV_SLOT_CSE 0x16 #define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0) #define PCH_DEVFN_CSE_2 _PCH_DEVFN(CSE, 1) -#define PCH_DEVFN_CSE_IDER _PCH_DEVFN(CSE, 2) -#define PCH_DEVFN_CSE_KT _PCH_DEVFN(CSE, 3) #define PCH_DEVFN_CSE_3 _PCH_DEVFN(CSE, 4) #define PCH_DEVFN_CSE_4 _PCH_DEVFN(CSE, 5) #define PCH_DEV_CSE _PCH_DEV(CSE, 0) #define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1) -#define PCH_DEV_CSE_IDER _PCH_DEV(CSE, 2) -#define PCH_DEV_CSE_KT _PCH_DEV(CSE, 3) #define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4) #define PCH_DEV_CSE_4 _PCH_DEV(CSE, 5) @@ -107,17 +89,19 @@ #define PCH_DEVFN_SATA _PCH_DEVFN(SATA, 0) #define PCH_DEV_SATA _PCH_DEV(SATA, 0) -#define PCH_DEV_SLOT_SIO4 0x19 -#define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO4, 0) -#define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO4, 1) -#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO4, 2) -#define PCH_DEV_I2C4 _PCH_DEV(SIO4, 0) -#define PCH_DEV_I2C5 _PCH_DEV(SIO4, 1) -#define PCH_DEV_UART2 _PCH_DEV(SIO4, 2) +#define PCH_DEV_SLOT_SIO2 0x19 +#define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO2, 0) +#define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO2, 1) +#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO2, 2) +#define PCH_DEV_I2C4 _PCH_DEV(SIO2, 0) +#define PCH_DEV_I2C5 _PCH_DEV(SIO2, 1) +#define PCH_DEV_UART2 _PCH_DEV(SIO2, 2) #define PCH_DEV_SLOT_STORAGE 0x1a #define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 0) +#define PCH_DEVFN_SDCARD _PCH_DEVFN(STORAGE, 1) #define PCH_DEV_EMMC _PCH_DEV(STORAGE, 0) +#define PCH_DEV_SDCARD _PCH_DEV(STORAGE, 1) #define PCH_DEV_SLOT_PCIE 0x1c #define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0) @@ -127,7 +111,6 @@ #define PCH_DEVFN_PCIE5 _PCH_DEVFN(PCIE, 4) #define PCH_DEVFN_PCIE6 _PCH_DEVFN(PCIE, 5) #define PCH_DEVFN_PCIE7 _PCH_DEVFN(PCIE, 6) -#define PCH_DEVFN_PCIE8 _PCH_DEVFN(PCIE, 7) #define PCH_DEV_PCIE1 _PCH_DEV(PCIE, 0) #define PCH_DEV_PCIE2 _PCH_DEV(PCIE, 1) #define PCH_DEV_PCIE3 _PCH_DEV(PCIE, 2) @@ -135,27 +118,22 @@ #define PCH_DEV_PCIE5 _PCH_DEV(PCIE, 4) #define PCH_DEV_PCIE6 _PCH_DEV(PCIE, 5) #define PCH_DEV_PCIE7 _PCH_DEV(PCIE, 6) -#define PCH_DEV_PCIE8 _PCH_DEV(PCIE, 7) - -#define PCH_DEV_SLOT_PCIE_1 0x1d -#define PCH_DEVFN_PCIE9 _PCH_DEVFN(PCIE_1, 0) -#define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1) -#define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2) -#define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3) -#define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0) -#define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1) -#define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2) -#define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3) - -#define PCH_DEV_SLOT_SIO5 0x1e -#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO5, 0) -#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO5, 1) -#define PCH_DEVFN_GSPI0 _PCH_DEVFN(SIO5, 2) -#define PCH_DEVFN_GSPI1 _PCH_DEVFN(SIO5, 3) -#define PCH_DEV_UART0 _PCH_DEV(SIO5, 0) -#define PCH_DEV_UART1 _PCH_DEV(SIO5, 1) -#define PCH_DEV_GSPI0 _PCH_DEV(SIO5, 2) -#define PCH_DEV_GSPI1 _PCH_DEV(SIO5, 3) + +#define PCH_DEV_SLOT_SIO3 0x1e +#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO3, 0) +#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO3, 1) +#define PCH_DEVFN_GSPI0 _PCH_DEVFN(SIO3, 2) +#define PCH_DEVFN_GSPI1 _PCH_DEVFN(SIO3, 3) +#define PCH_DEVFN_GBE _PCH_DEVFN(SIO3, 4) +#define PCH_DEVFN_HPET _PCH_DEVFN(SIO3, 6) +#define PCH_DEVFN_IOAPIC _PCH_DEVFN(SIO3, 7) +#define PCH_DEV_UART0 _PCH_DEV(SIO3, 0) +#define PCH_DEV_UART1 _PCH_DEV(SIO3, 1) +#define PCH_DEV_GSPI0 _PCH_DEV(SIO3, 2) +#define PCH_DEV_GSPI1 _PCH_DEV(SIO3, 3) +#define PCH_DEV_GBE _PCH_DEV(SIO3, 4) +#define PCH_DEV_HPET _PCH_DEV(SIO3, 6) +#define PCH_DEV_IOAPIC _PCH_DEV(SIO3, 7) #define PCH_DEV_SLOT_ESPI 0x1f #define PCH_DEV_SLOT_LPC PCH_DEV_SLOT_ESPI @@ -165,7 +143,6 @@ #define PCH_DEVFN_HDA _PCH_DEVFN(ESPI, 3) #define PCH_DEVFN_SMBUS _PCH_DEVFN(ESPI, 4) #define PCH_DEVFN_SPI _PCH_DEVFN(ESPI, 5) -#define PCH_DEVFN_GBE _PCH_DEVFN(ESPI, 6) #define PCH_DEVFN_TRACEHUB _PCH_DEVFN(ESPI, 7) #define PCH_DEV_ESPI _PCH_DEV(ESPI, 0) #define PCH_DEV_LPC PCH_DEV_ESPI @@ -186,7 +163,6 @@ #define PCH_DEV_HDA _PCH_DEV(ESPI, 3) #define PCH_DEV_SMBUS _PCH_DEV(ESPI, 4) #define PCH_DEV_SPI _PCH_DEV(ESPI, 5) -#define PCH_DEV_GBE _PCH_DEV(ESPI, 6) #define PCH_DEV_TRACEHUB _PCH_DEV(ESPI, 7) #endif |