5 files changed, 0 insertions, 92 deletions

diff --git a/src/soc/intel/xeon_sp/ibl/include/soc/azalia_device.h b/src/soc/intel/xeon_sp/ibl/include/soc/azalia_device.h
deleted file mode 100644
index 911ff15203..0000000000
--- a/src/soc/intel/xeon_sp/ibl/include/soc/azalia_device.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef DEVICE_AZALIA_H
-#define DEVICE_AZALIA_H
-
-#define HDA_PCS			0x54
-#define  HDA_PCS_PS_D3HOT	3
-
-#endif /* DEVICE_AZALIA_H */
diff --git a/src/soc/intel/xeon_sp/ibl/include/soc/pcr_ids.h b/src/soc/intel/xeon_sp/ibl/include/soc/pcr_ids.h
index f4276c9de6..73b12b35a0 100644
--- a/src/soc/intel/xeon_sp/ibl/include/soc/pcr_ids.h
+++ b/src/soc/intel/xeon_sp/ibl/include/soc/pcr_ids.h
@@ -5,11 +5,8 @@
 
 #define PID_NOT_SUPPORTED 0xff
 #define PID_ITSS          0x00
-#define PID_IOTRAP        0x01
 #define PID_RTC           PID_NOT_SUPPORTED
-#define PID_DMI           PID_NOT_SUPPORTED
 #define PID_PSF3          PID_NOT_SUPPORTED
-#define PID_ESPI          0x02
 #define PID_GPIOCOM0      0x03
 #define PID_GPIOCOM5      PID_NOT_SUPPORTED
 #define PID_GPIOCOM4      PID_NOT_SUPPORTED
diff --git a/src/soc/intel/xeon_sp/ibl/include/soc/pmc.h b/src/soc/intel/xeon_sp/ibl/include/soc/pmc.h
index 09bfbdbb30..f36435dd2f 100644
--- a/src/soc/intel/xeon_sp/ibl/include/soc/pmc.h
+++ b/src/soc/intel/xeon_sp/ibl/include/soc/pmc.h
@@ -9,25 +9,17 @@
 /* Memory mapped IO registers in PMC */
 #define GEN_PMCON_A		0x1020
 #define  GBL_RST_STS		(1 << 24)
-#define  DISB			(1 << 23)
 #define  MS4V			(1 << 18)
 #define  SUS_PWR_FLR		(1 << 16)
 #define  PWR_FLR		(1 << 14)
-#define  HOST_RST_STS		(1 << 9)
 #define  PER_SMI_SEL_MASK	(3 << 1)
 #define    SMI_RATE_64S		(0 << 1)
-#define    SMI_RATE_32S		(1 << 1)
-#define    SMI_RATE_16S		(2 << 1)
-#define    SMI_RATE_8S		(3 << 1)
 #define  SLEEP_AFTER_POWER_FAIL	(1 << 0)
 #define GEN_PMCON_B		0x1024
 #define  SLP_STR_POL_LOCK	(1 << 18)
-#define  SMI_LOCK		(1 << 4)
 #define  RTC_BATTERY_DEAD	(1 << 2)
 #define PM_CFG			0x1818
 #define  PMC_LOCK		(1 << 27)
-#define PMSYNC_MISC_CFG		0x18c8
-#define  PMSYNC_LOCK		(1 << 15)
 #define PCH_PWRM_ACPI_TMR_CTL	0x18fc
 #define  ACPI_TIM_DIS		(1 << 1)
 #define GPIO_GPE_CFG		0x1920
@@ -35,10 +27,7 @@
 #define GPE0_DW_SHIFT(x)	(4 * (x))
 #define GBLRST_CAUSE0		0x1924
 #define GBLRST_CAUSE1		0x1928
-#define ACTL			0x1BD8
 #define PMC_ACPI_CNT		0x44
-#define  PWRM_EN		(1 << 8)
-#define  ACPI_EN		(1 << 7)
 #define  SCI_IRQ_SEL		(7 << 0)
 #define  SCI_IRQ_ADJUST		0
 #define  SCIS_IRQ9		0
@@ -48,9 +37,5 @@
 #define  SCIS_IRQ21		5
 #define  SCIS_IRQ22		6
 #define  SCIS_IRQ23		7
-#define ST_PG_FDIS1		0x1e20
-#define  ST_FDIS_LK		(1 << 31)
-#define NST_PG_FDIS1		0x1e28
-#define  NST_FDIS_DSP		(1 << 23)
 
 #endif
diff --git a/src/soc/intel/xeon_sp/ibl/soc_pch.c b/src/soc/intel/xeon_sp/ibl/soc_pch.c
index a40af7abc7..6bfa7493ce 100644
--- a/src/soc/intel/xeon_sp/ibl/soc_pch.c
+++ b/src/soc/intel/xeon_sp/ibl/soc_pch.c
@@ -4,24 +4,13 @@
 #include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>
 #include <intelblocks/pcr.h>
-#include <intelblocks/pmclib.h>
-#include <intelblocks/rtc.h>
-#include <intelblocks/p2sb.h>
-#include <soc/azalia_device.h>
 #include <soc/bootblock.h>
-#include <soc/soc_pch.h>
-#include <soc/pch.h>
-#include <soc/pmc.h>
 #include <console/console.h>
 
 #define PCR_PSF3_TO_SHDW_PMC_REG_BASE	0x600
 #define PCR_PSFX_TO_SHDW_BAR4		0x10
 #define PCR_PSFX_TO_SHDW_PCIEN_IOEN	0x01
 #define PCR_PSFX_T0_SHDW_PCIEN		0x1C
-#define PCR_DMI_MISC_PORT_CFG		0x20D8
-#define  MISC_PORT_CFG_LOCK		BIT(23)
-#define PCR_DMI_DMICTL		0x2234
-#define  PCR_DMI_DMICTL_SRLOCK	(1 << 31)
 
 static void soc_config_acpibase(void)
 {
@@ -55,30 +44,3 @@ void bootblock_pch_init(void)
 	 */
 	soc_config_acpibase();
 }
-
-void pch_lock_dmictl(void)
-{
-	uint32_t reg32 = pcr_read32(PID_DMI, PCR_DMI_DMICTL);
-	pcr_write32(PID_DMI, PCR_DMI_DMICTL, reg32 | PCR_DMI_DMICTL_SRLOCK);
-	pcr_or32(PID_DMI, PCR_DMI_MISC_PORT_CFG, MISC_PORT_CFG_LOCK);
-}
-
-#define PCR_PSFX_T0_SHDW_PCIEN		0x1C
-#define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS	(1 << 8)
-#define PSF3_HDA_BASE_ADDRESS		0x280
-
-void pch_disable_hda(void)
-{
-	/* Ensure memory, io, and bus master are all disabled */
-	pci_and_config16(PCH_DEV_HDA, PCI_COMMAND, ~(PCI_COMMAND_MASTER |
-			 PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
-	/* Put controller to D3 */
-	pci_or_config32(PCH_DEV_HDA, HDA_PCS, HDA_PCS_PS_D3HOT);
-	/* Disable DSP in PMC */
-	pmc_or_mmio32(NST_PG_FDIS1, NST_FDIS_DSP);
-	/* Hide PCI function */
-	pcr_or32(PID_PSF3, PSF3_HDA_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN,
-		 PCR_PSFX_T0_SHDW_PCIEN_FUNDIS);
-
-	printk(BIOS_INFO, "%s: Disabled HDA device 00:1f.3\n", __func__);
-}
diff --git a/src/soc/intel/xeon_sp/ibl/soc_pmutil.c b/src/soc/intel/xeon_sp/ibl/soc_pmutil.c
index 7160dee791..406114e6ac 100644
--- a/src/soc/intel/xeon_sp/ibl/soc_pmutil.c
+++ b/src/soc/intel/xeon_sp/ibl/soc_pmutil.c
@@ -47,23 +47,6 @@ int soc_get_rtc_failed(void)
 	return rtc_fail;
 }
 
-void soc_fill_power_state(struct chipset_power_state *ps)
-{
-	uint8_t *pmc;
-
-	pmc = pmc_mmio_regs();
-
-	ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);
-	ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B);
-	ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
-	ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
-
-	printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", ps->gen_pmcon_a, ps->gen_pmcon_b);
-
-	printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", ps->gblrst_cause[0],
-	       ps->gblrst_cause[1]);
-}
-
 /*
  * Set which power state system will be after reapplying
  * the power (from G3 State)
@@ -81,22 +64,12 @@ void pmc_soc_set_afterg3_en(const bool on)
 	write8(pmcbase + GEN_PMCON_A, reg8);
 }
 
-void pmc_lock_smi(void)
-{
-	printk(BIOS_DEBUG, "Locking SMM enable.\n");
-	pmc_or_mmio32(GEN_PMCON_B, SMI_LOCK);
-}
-
 void pmc_lockdown_config(void)
 {
-	/* PMSYNC */
-	pmc_or_mmio32(PMSYNC_MISC_CFG, PMSYNC_LOCK);
-
 	/* Make sure payload/OS can't trigger global reset */
 	pmc_global_reset_disable_and_lock();
 
 	/* Lock PMC stretch policy */
 	pmc_or_mmio32(GEN_PMCON_B, SLP_STR_POL_LOCK);
-	pmc_or_mmio32(ST_PG_FDIS1, ST_FDIS_LK);
 	pmc_or_mmio32(PM_CFG, PMC_LOCK);
 }