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-rw-r--r--src/soc/intel/cannonlake/acpi/pcr.asl23
-rw-r--r--src/soc/intel/cannonlake/acpi/southbridge.asl2
2 files changed, 1 insertions, 24 deletions
diff --git a/src/soc/intel/cannonlake/acpi/pcr.asl b/src/soc/intel/cannonlake/acpi/pcr.asl
deleted file mode 100644
index 7915226a0a..0000000000
--- a/src/soc/intel/cannonlake/acpi/pcr.asl
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- * Copyright (C) 2017 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <intelblocks/pcr.h>
-
-Method (PCRB, 1, NotSerialized)
-{
- Return (Add (CONFIG_PCR_BASE_ADDRESS,
- ShiftLeft (Arg0, PCR_PORTID_SHIFT)))
-}
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl
index d0d03f0ac3..8d74da9f42 100644
--- a/src/soc/intel/cannonlake/acpi/southbridge.asl
+++ b/src/soc/intel/cannonlake/acpi/southbridge.asl
@@ -23,7 +23,7 @@
#include "scs.asl"
/* PCR access */
-#include "pcr.asl"
+#include <soc/intel/common/acpi/pcr.asl>
/* GPIO controller */
#include "gpio.asl"