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-rw-r--r--src/soc/intel/tigerlake/acpi/gpio.asl150
-rw-r--r--src/soc/intel/tigerlake/gpio.c102
-rw-r--r--src/soc/intel/tigerlake/include/soc/gpio.h7
-rw-r--r--src/soc/intel/tigerlake/include/soc/gpio_defs.h454
-rw-r--r--src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h549
5 files changed, 711 insertions, 551 deletions
diff --git a/src/soc/intel/tigerlake/acpi/gpio.asl b/src/soc/intel/tigerlake/acpi/gpio.asl
index 98863e2486..dc76a387b7 100644
--- a/src/soc/intel/tigerlake/acpi/gpio.asl
+++ b/src/soc/intel/tigerlake/acpi/gpio.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
+ * Copyright (C) 2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -16,60 +16,97 @@
#include <soc/irq.h>
#include <soc/pcr_ids.h>
-
-Device (GPIO)
+Device (GCM0)
{
- Name (_HID, "INT3455")
+ Name (_HID, "INT34C5")
Name (_UID, 0)
- Name (_DDN, "GPIO Controller")
+ Name (_DDN, "GPIO Controller Community 0")
+ Name (RBUF, ResourceTemplate()
+ {
+ Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM0)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+ { GPIO_IRQ14 }
+ })
Method (_CRS, 0, NotSerialized)
{
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0, COM0)
- Memory32Fixed (ReadWrite, 0, 0, COM1)
- Memory32Fixed (ReadWrite, 0, 0, COM2)
- Memory32Fixed (ReadWrite, 0, 0, COM4)
- Memory32Fixed (ReadWrite, 0, 0, COM5)
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
- { GPIO_IRQ14 }
- })
+ CreateDWordField (^RBUF, ^COM0._BAS, BAS0)
+ BAS0 = ^^PCRB (PID_GPIOCOM0)
+ Return (^RBUF)
+ }
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+}
- /* GPIO Community 0 */
- CreateDWordField (RBUF, COM0._BAS, BAS0)
- CreateDWordField (RBUF, COM0._LEN, LEN0)
- Store (PCRB (PID_GPIOCOM0), BAS0)
- Store (GPIO_BASE_SIZE, LEN0)
+Device (GCM1)
+{
+ Name (_HID, "INT34C5")
+ Name (_UID, 1)
+ Name (_DDN, "GPIO Controller Community 1")
- /* GPIO Community 1 */
- CreateDWordField (RBUF, COM1._BAS, BAS1)
- CreateDWordField ( RBUF, COM1._LEN, LEN1)
- Store (PCRB (PID_GPIOCOM1), BAS1)
- Store (GPIO_BASE_SIZE, LEN1)
+ Name (RBUF, ResourceTemplate()
+ {
+ Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM1)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+ { GPIO_IRQ14 }
+ })
+ Method (_CRS, 0, NotSerialized)
+ {
+ CreateDWordField (^RBUF, ^COM1._BAS, BAS1)
+ BAS1 = ^^PCRB (PID_GPIOCOM1)
+ Return (^RBUF)
+ }
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+}
- /* GPIO Community 2 */
- CreateDWordField (RBUF, COM2._BAS, BAS2)
- CreateDWordField (RBUF, COM2._LEN, LEN2)
- Store (PCRB (PID_GPIOCOM2), BAS2)
- Store (GPIO_BASE_SIZE, LEN2)
+Device (GCM4)
+{
+ Name (_HID, "INT34C5")
+ Name (_UID, 4)
+ Name (_DDN, "GPIO Controller Community 4")
- /* GPIO Community 4 */
- CreateDWordField (RBUF, COM4._BAS, BAS4)
- CreateDWordField (RBUF, COM4._LEN, LEN4)
- Store (PCRB (PID_GPIOCOM4), BAS4)
- Store (GPIO_BASE_SIZE, LEN4)
+ Name (RBUF, ResourceTemplate()
+ {
+ Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM4)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+ { GPIO_IRQ14 }
+ })
+ Method (_CRS, 0, NotSerialized)
+ {
+ CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
+ BAS4 = ^^PCRB (PID_GPIOCOM4)
+ Return (^RBUF)
+ }
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+}
- /* GPIO Community 5 */
- CreateDWordField (RBUF, COM5._BAS, BAS5)
- CreateDWordField (RBUF, COM5._LEN, LEN5)
- Store (PCRB (PID_GPIOCOM5), BAS5)
- Store (GPIO_BASE_SIZE, LEN5)
+Device (GCM5)
+{
+ Name (_HID, "INT34C5")
+ Name (_UID, 5)
+ Name (_DDN, "GPIO Controller Community 5")
- Return (RBUF)
+ Name (RBUF, ResourceTemplate()
+ {
+ Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM5)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+ { GPIO_IRQ14 }
+ })
+ Method (_CRS, 0, NotSerialized)
+ {
+ CreateDWordField (^RBUF, ^COM5._BAS, BAS5)
+ BAS5 = ^^PCRB (PID_GPIOCOM5)
+ Return (^RBUF)
}
-
- Method (_STA, 0, NotSerialized)
+ Method (_STA)
{
Return (0xF)
}
@@ -82,38 +119,37 @@ Device (GPIO)
Method (GADD, 1, NotSerialized)
{
/* GPIO Community 0 */
- If (Arg0 >= GPP_G0 && Arg0 <= GPP_A23)
+ If (Arg0 >= GPP_B0 && Arg0 <= GPP_A24)
{
Local0 = PID_GPIOCOM0
- Subtract (Arg0, GPP_A0, Local1)
+ Local1 = Arg0 - GPP_B0
}
/* GPIO Community 1 */
- If (Arg0 >= GPP_H0 && Arg0 <= GPP_F19)
+ If (Arg0 >= GPP_S0 && Arg0 <= vI2S2_RXD)
{
Local0 = PID_GPIOCOM1
- Subtract (Arg0, GPP_D0, Local1)
+ Local1 = Arg0 - GPP_S0
}
/* GPIO Community 2 */
- If (Arg0 >= GPD0 && Arg0 <= GPD11)
+ If (Arg0 >= GPD0 && Arg0 <= GPD_DRAM_RESETB)
{
Local0 = PID_GPIOCOM2
- Subtract (Arg0, GPD0, Local1)
+ Local1 = Arg0 - GPD0
}
/* GPIO Community 4 */
- If (Arg0 >= GPP_C0 && Arg0 <= GPP_E23)
+ If (Arg0 >= GPP_C0 && Arg0 <= GPP_DBG_PMODE)
{
Local0 = PID_GPIOCOM4
- Subtract (Arg0, GPP_C0, Local1)
+ Local1 = Arg0 - GPP_C0
}
- /* GPIO Community 05*/
- If (Arg0 >= GPP_R0 && Arg0 <= GPP_S7)
+ /* GPIO Community 5 */
+ If (Arg0 >= GPP_R0 && Arg0 <= GPP_CLK_LOOPBK)
{
Local0 = PID_GPIOCOM5
- Subtract (Arg0, GPP_R0, Local1)
+ Local1 = Arg0 - GPP_R0
}
- Store (PCRB (Local0), Local2)
- Add (Local2, PAD_CFG_BASE, Local2)
- Return (Add (Local2, Multiply (Local1, 16)))
+ Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16)
+ Return (Local2)
}
/*
diff --git a/src/soc/intel/tigerlake/gpio.c b/src/soc/intel/tigerlake/gpio.c
index 18b90702c1..5b06b30d79 100644
--- a/src/soc/intel/tigerlake/gpio.c
+++ b/src/soc/intel/tigerlake/gpio.c
@@ -14,24 +14,23 @@
* GNU General Public License for more details.
*/
+#include <intelblocks/gpio.h>
+#include <intelblocks/pcr.h>
+#include <soc/pcr_ids.h>
+#include <soc/pmc.h>
+
/*
* This file is created based on Intel Tiger Lake Processor PCH Datasheet
* Document number: 575857
* Chapter number: 27
*/
-#include <intelblocks/gpio.h>
-#include <intelblocks/pcr.h>
-#include <soc/pcr_ids.h>
-#include <soc/pmc.h>
-
static const struct reset_mapping rst_map[] = {
{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
};
-
-static const struct reset_mapping rst_map_com0[] = {
+static const struct reset_mapping rst_map_com2[] = {
{ .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
@@ -39,55 +38,46 @@ static const struct reset_mapping rst_map_com0[] = {
};
/*
- * The GPIO driver for Tigerlake on Windows/Linux expects 32 GPIOs per pad
- * group, regardless of whether or not there is a physical pad for each
- * exposed GPIO number.
- *
- * This results in the OS having a sparse GPIO map, and devices that need
- * to export an ACPI GPIO must use the OS expected number.
- *
- * Not all pins are usable as GPIO and those groups do not have a pad base.
- *
- * This layout matches the Linux kernel pinctrl map for CNL-LP at:
+ * This layout matches the Linux kernel pinctrl map for TGL-LP at:
* linux/drivers/pinctrl/intel/pinctrl-tigerlake.c
*/
static const struct pad_group tgl_community0_groups[] = {
- INTEL_GPP_BASE(GPP_G0, GPP_G0, GPP_G7, 0), /* GPP_G */
- INTEL_GPP_BASE(GPP_G0, GPP_B0, GPP_B23, 32), /* GPP_B */
- INTEL_GPP(GPP_G0, GPIO_RSVD_0, GPIO_RSVD_1),
- INTEL_GPP_BASE(GPP_G0, GPP_A0, GPP_A23, 64), /* GPP_A */
+ INTEL_GPP(GPP_B0, GPP_B0, GPP_B25), /* GPP_B */
+ INTEL_GPP(GPP_B0, GPP_T0, GPP_T15), /* GPP_T */
+ INTEL_GPP(GPP_B0, GPP_A0, GPP_A24), /* GPP_A */
};
static const struct pad_group tgl_community1_groups[] = {
- INTEL_GPP_BASE(GPP_H0, GPP_H0, GPP_H23, 96), /* GPP_H */
- INTEL_GPP_BASE(GPP_H0, GPP_D0, GPIO_RSVD_2, 128), /* GPP_D */
- INTEL_GPP_BASE(GPP_H0, GPP_F0, GPP_F19, 160), /* GPP_F */
+ INTEL_GPP(GPP_S0, GPP_S0, GPP_S7), /* GPP_S */
+ INTEL_GPP(GPP_S0, GPP_H0, GPP_H23), /* GPP_H */
+ INTEL_GPP(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK), /* GPP_D */
+ INTEL_GPP(GPP_S0, GPP_U0, GPP_GSPI6_CLK_LOOPBK), /* GPP_U */
+ INTEL_GPP(GPP_S0, CNV_BTEN, vI2S2_RXD), /* GPP_VGPIO */
};
/* This community is not visible to the OS */
static const struct pad_group tgl_community2_groups[] = {
- INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */
+ INTEL_GPP(GPD0, GPD0, GPD_DRAM_RESETB), /* GPD */
};
-
static const struct pad_group tgl_community4_groups[] = {
- INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 224), /* GPP_C */
- INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E23, 256), /* GPP_E */
- INTEL_GPP(GPP_C0, GPIO_RSVD_3, GPIO_RSVD_8),
+ INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP_C */
+ INTEL_GPP(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK), /* GPP_F */
+ INTEL_GPP(GPP_C0, GPP_L_BKLTEN, GPP_MLK_RSTB), /* GPP_HVCMOS */
+ INTEL_GPP(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK), /* GPP_E */
+ INTEL_GPP(GPP_C0, GPP_JTAG_TDO, GPP_DBG_PMODE), /* GPP_JTAG */
};
-
static const struct pad_group tgl_community5_groups[] = {
- INTEL_GPP_BASE(GPP_R0, GPP_R0, GPP_R7, 288), /* GPP_R */
- INTEL_GPP_BASE(GPP_C0, GPP_S0, GPP_S7, 320), /* GPP_S */
+ INTEL_GPP(GPP_R0, GPP_R0, GPP_R7), /* GPP_R */
+ INTEL_GPP(GPP_R0, GPP_SPI_IO_2, GPP_CLK_LOOPBK), /* GPP_SPI */
};
-static const struct pad_community tgl_communities[TOTAL_GPIO_COMM] = {
- /* GPP G, B, A */
- [COMM_0] = {
+static const struct pad_community tgl_communities[] = {
+ [COMM_0] = { /* GPP B, T, A */
.port = PID_GPIOCOM0,
- .first_pad = GPP_G0,
- .last_pad = GPP_A23,
+ .first_pad = GPP_B0,
+ .last_pad = GPP_A24,
.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
@@ -96,18 +86,17 @@ static const struct pad_community tgl_communities[TOTAL_GPIO_COMM] = {
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
- .name = "GPP_GBA",
+ .name = "GPP_BTA",
.acpi_path = "\\_SB.PCI0.GPIO",
- .reset_map = rst_map_com0,
- .num_reset_vals = ARRAY_SIZE(rst_map_com0),
+ .reset_map = rst_map,
+ .num_reset_vals = ARRAY_SIZE(rst_map),
.groups = tgl_community0_groups,
.num_groups = ARRAY_SIZE(tgl_community0_groups),
},
- /* GPP H, D, F */
- [COMM_1] = {
+ [COMM_1] = { /* GPP S, D, H, U, VGPIO */
.port = PID_GPIOCOM1,
- .first_pad = GPP_H0,
- .last_pad = GPP_F19,
+ .first_pad = GPP_S0,
+ .last_pad = vI2S2_RXD,
.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
@@ -116,18 +105,17 @@ static const struct pad_community tgl_communities[TOTAL_GPIO_COMM] = {
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
- .name = "GPP_HDF",
+ .name = "GPP_SDHU",
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map,
.num_reset_vals = ARRAY_SIZE(rst_map),
.groups = tgl_community1_groups,
.num_groups = ARRAY_SIZE(tgl_community1_groups),
},
- /* GPD */
- [COMM_2] = {
+ [COMM_2] = { /* GPD */
.port = PID_GPIOCOM2,
.first_pad = GPD0,
- .last_pad = GPD11,
+ .last_pad = GPD_DRAM_RESETB,
.num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
@@ -138,16 +126,15 @@ static const struct pad_community tgl_communities[TOTAL_GPIO_COMM] = {
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPD",
.acpi_path = "\\_SB.PCI0.GPIO",
- .reset_map = rst_map,
- .num_reset_vals = ARRAY_SIZE(rst_map),
+ .reset_map = rst_map_com2,
+ .num_reset_vals = ARRAY_SIZE(rst_map_com2),
.groups = tgl_community2_groups,
.num_groups = ARRAY_SIZE(tgl_community2_groups),
},
- /* GPP C, E */
- [COMM_3] = {
+ [COMM_4] = { /* GPP F, C, HVCOS, E, JTAG */
.port = PID_GPIOCOM4,
.first_pad = GPP_C0,
- .last_pad = GPP_E23,
+ .last_pad = GPP_DBG_PMODE,
.num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
@@ -156,18 +143,17 @@ static const struct pad_community tgl_communities[TOTAL_GPIO_COMM] = {
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
- .name = "GPP_CE",
+ .name = "GPP_FCE",
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map,
.num_reset_vals = ARRAY_SIZE(rst_map),
.groups = tgl_community4_groups,
.num_groups = ARRAY_SIZE(tgl_community4_groups),
},
- /* GPP R, S */
- [COMM_4] = {
+ [COMM_5] = { /* GPP R, SPI */
.port = PID_GPIOCOM5,
.first_pad = GPP_R0,
- .last_pad = GPP_S7,
+ .last_pad = GPP_CLK_LOOPBK,
.num_gpi_regs = NUM_GPIO_COM5_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
@@ -176,7 +162,7 @@ static const struct pad_community tgl_communities[TOTAL_GPIO_COMM] = {
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
- .name = "GPP_RS",
+ .name = "GPP_CPU_VBPIO",
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map,
.num_reset_vals = ARRAY_SIZE(rst_map),
diff --git a/src/soc/intel/tigerlake/include/soc/gpio.h b/src/soc/intel/tigerlake/include/soc/gpio.h
index 4b359b7452..ccc274ba3e 100644
--- a/src/soc/intel/tigerlake/include/soc/gpio.h
+++ b/src/soc/intel/tigerlake/include/soc/gpio.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2018 Intel Corp.
+ * Copyright (C) 2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -19,6 +19,9 @@
#include <soc/gpio_defs.h>
#include <intelblocks/gpio.h>
-#define CROS_GPIO_DEVICE_NAME "INT3455:00"
+#define CROS_GPIO_COMM0_NAME "INT34C5:00"
+#define CROS_GPIO_COMM1_NAME "INT34C5:01"
+#define CROS_GPIO_COMM4_NAME "INT34C5:02"
+#define CROS_GPIO_COMM5_NAME "INT34C5:03"
#endif
diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_defs.h
index bffebcd312..6a5a6e2329 100644
--- a/src/soc/intel/tigerlake/include/soc/gpio_defs.h
+++ b/src/soc/intel/tigerlake/include/soc/gpio_defs.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2018 Intel Corp.
+ * Copyright (C) 2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -21,7 +21,6 @@
#endif
#include <soc/gpio_soc_defs.h>
-
#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */
#define NUM_GPIO_COMx_GPI_REGS(n) \
@@ -43,222 +42,264 @@
* IOxAPIC IRQs for the GPIOs
*/
-/* Group G */
-#define GPP_G0_IRQ 0x18
-#define GPP_G1_IRQ 0x19
-#define GPP_G2_IRQ 0x1a
-#define GPP_G3_IRQ 0x1b
-#define GPP_G4_IRQ 0x1c
-#define GPP_G5_IRQ 0x1d
-#define GPP_G6_IRQ 0x1e
-#define GPP_G7_IRQ 0x1f
-
/* Group B */
-#define GPP_B0_IRQ 0x20
-#define GPP_B1_IRQ 0x21
-#define GPP_B2_IRQ 0x22
-#define GPP_B3_IRQ 0x23
-#define GPP_B4_IRQ 0x24
-#define GPP_B5_IRQ 0x25
-#define GPP_B6_IRQ 0x26
-#define GPP_B7_IRQ 0x27
-#define GPP_B8_IRQ 0x28
-#define GPP_B9_IRQ 0x29
-#define GPP_B10_IRQ 0x2a
-#define GPP_B11_IRQ 0x2b
-#define GPP_B12_IRQ 0x2c
-#define GPP_B13_IRQ 0x2d
-#define GPP_B14_IRQ 0x2e
-#define GPP_B15_IRQ 0x2f
-#define GPP_B16_IRQ 0x30
-#define GPP_B17_IRQ 0x31
-#define GPP_B18_IRQ 0x32
-#define GPP_B19_IRQ 0x33
-#define GPP_B20_IRQ 0x34
-#define GPP_B21_IRQ 0x35
-#define GPP_B22_IRQ 0x36
-#define GPP_B23_IRQ 0x37
+#define GPP_B0_IRQ 0x18
+#define GPP_B1_IRQ 0x19
+#define GPP_B2_IRQ 0x1A
+#define GPP_B3_IRQ 0x1B
+#define GPP_B4_IRQ 0x1C
+#define GPP_B5_IRQ 0x1D
+#define GPP_B6_IRQ 0x1E
+#define GPP_B7_IRQ 0x1F
+#define GPP_B8_IRQ 0x20
+#define GPP_B9_IRQ 0x21
+#define GPP_B10_IRQ 0x22
+#define GPP_B11_IRQ 0x23
+#define GPP_B12_IRQ 0x24
+#define GPP_B13_IRQ 0x25
+#define GPP_B14_IRQ 0x26
+#define GPP_B15_IRQ 0x27
+#define GPP_B16_IRQ 0x28
+#define GPP_B17_IRQ 0x29
+#define GPP_B18_IRQ 0x2A
+#define GPP_B19_IRQ 0x2B
+#define GPP_B20_IRQ 0x2C
+#define GPP_B21_IRQ 0x2D
+#define GPP_B22_IRQ 0x2E
+#define GPP_B23_IRQ 0x2F
+
+/* Group T */
+#define GPP_T0_IRQ 0x30
+#define GPP_T1_IRQ 0x31
+#define GPP_T2_IRQ 0x32
+#define GPP_T3_IRQ 0x33
+#define GPP_T4_IRQ 0x34
+#define GPP_T5_IRQ 0x35
+#define GPP_T6_IRQ 0x36
+#define GPP_T7_IRQ 0x37
+#define GPP_T8_IRQ 0x38
+#define GPP_T9_IRQ 0x39
+#define GPP_T10_IRQ 0x3A
+#define GPP_T11IRQ 0x3B
+#define GPP_T12_IRQ 0x3C
+#define GPP_T13_IRQ 0x3D
+#define GPP_T14_IRQ 0x3E
+#define GPP_T15_IRQ 0x3F
/* Group A */
-#define GPP_A0_IRQ 0x38
-#define GPP_A1_IRQ 0x39
-#define GPP_A2_IRQ 0x3a
-#define GPP_A3_IRQ 0x3b
-#define GPP_A4_IRQ 0x3c
-#define GPP_A5_IRQ 0x3d
-#define GPP_A6_IRQ 0x3e
-#define GPP_A7_IRQ 0x3f
-#define GPP_A8_IRQ 0x40
-#define GPP_A9_IRQ 0x41
-#define GPP_A10_IRQ 0x42
-#define GPP_A11_IRQ 0x43
-#define GPP_A12_IRQ 0x44
-#define GPP_A13_IRQ 0x45
-#define GPP_A14_IRQ 0x46
-#define GPP_A15_IRQ 0x47
-#define GPP_A16_IRQ 0x48
-#define GPP_A17_IRQ 0x49
-#define GPP_A18_IRQ 0x4a
-#define GPP_A19_IRQ 0x4b
-#define GPP_A20_IRQ 0x4c
-#define GPP_A21_IRQ 0x4d
-#define GPP_A22_IRQ 0x4e
-#define GPP_A23_IRQ 0x4f
+#define GPP_A0_IRQ 0x40
+#define GPP_A1_IRQ 0x41
+#define GPP_A2_IRQ 0x42
+#define GPP_A3_IRQ 0x43
+#define GPP_A4_IRQ 0x44
+#define GPP_A5_IRQ 0x45
+#define GPP_A6_IRQ 0x46
+#define GPP_A7_IRQ 0x47
+#define GPP_A8_IRQ 0x48
+#define GPP_A9_IRQ 0x49
+#define GPP_A10_IRQ 0x4A
+#define GPP_A11_IRQ 0x4B
+#define GPP_A12_IRQ 0x4C
+#define GPP_A13_IRQ 0x4D
+#define GPP_A14_IRQ 0x4E
+#define GPP_A15_IRQ 0x4F
+#define GPP_A16_IRQ 0x50
+#define GPP_A17_IRQ 0x51
+#define GPP_A18_IRQ 0x52
+#define GPP_A19_IRQ 0x53
+#define GPP_A20_IRQ 0x54
+#define GPP_A21_IRQ 0x55
+#define GPP_A22_IRQ 0x56
+#define GPP_A23_IRQ 0x57
+
+/* Group R */
+#define GPP_R0_IRQ 0x58
+#define GPP_R1_IRQ 0x59
+#define GPP_R2_IRQ 0x5A
+#define GPP_R3_IRQ 0x5B
+#define GPP_R4_IRQ 0x5C
+#define GPP_R5_IRQ 0x5D
+#define GPP_R6_IRQ 0x5E
+#define GPP_R7_IRQ 0x5F
+
+
+/* Group D */
+#define GPD0_IRQ 0x60
+#define GPD1_IRQ 0x61
+#define GPD2_IRQ 0x62
+#define GPD3_IRQ 0x63
+#define GPD4_IRQ 0x64
+#define GPD5_IRQ 0x65
+#define GPD6_IRQ 0x66
+#define GPD7_IRQ 0x67
+#define GPD8_IRQ 0x68
+#define GPD9_IRQ 0x69
+#define GPD10_IRQ 0x6A
+#define GPD11_IRQ 0x6B
+
+/* Group S */
+#define GPP_S0_IRQ 0x6C
+#define GPP_S1_IRQ 0x6D
+#define GPP_S2_IRQ 0x6E
+#define GPP_S3_IRQ 0x6F
+#define GPP_S4_IRQ 0x70
+#define GPP_S5_IRQ 0x71
+#define GPP_S6_IRQ 0x72
+#define GPP_S7_IRQ 0x73
/* Group H */
-#define GPP_H0_IRQ 0x70
-#define GPP_H1_IRQ 0x71
-#define GPP_H2_IRQ 0x72
-#define GPP_H3_IRQ 0x73
-#define GPP_H4_IRQ 0x74
-#define GPP_H5_IRQ 0x75
-#define GPP_H6_IRQ 0x76
-#define GPP_H7_IRQ 0x77
-#define GPP_H8_IRQ 0x18
-#define GPP_H9_IRQ 0x19
-#define GPP_H10_IRQ 0x1a
-#define GPP_H11_IRQ 0x1b
-#define GPP_H12_IRQ 0x1c
-#define GPP_H13_IRQ 0x1d
-#define GPP_H14_IRQ 0x1e
-#define GPP_H15_IRQ 0x1f
-#define GPP_H16_IRQ 0x20
-#define GPP_H17_IRQ 0x21
-#define GPP_H18_IRQ 0x22
-#define GPP_H19_IRQ 0x23
-#define GPP_H20_IRQ 0x24
-#define GPP_H21_IRQ 0x25
-#define GPP_H22_IRQ 0x26
-#define GPP_H23_IRQ 0x27
+#define GPP_H0_IRQ 0x74
+#define GPP_H1_IRQ 0x75
+#define GPP_H2_IRQ 0x76
+#define GPP_H3_IRQ 0x77
+#define GPP_H4_IRQ 0x18
+#define GPP_H5_IRQ 0x19
+#define GPP_H6_IRQ 0x1A
+#define GPP_H7_IRQ 0x1B
+#define GPP_H8_IRQ 0x1C
+#define GPP_H9_IRQ 0x1D
+#define GPP_H10_IRQ 0x1E
+#define GPP_H11_IRQ 0x1F
+#define GPP_H12_IRQ 0x20
+#define GPP_H13_IRQ 0x21
+#define GPP_H14_IRQ 0x22
+#define GPP_H15_IRQ 0x23
+#define GPP_H16_IRQ 0x24
+#define GPP_H17_IRQ 0x25
+#define GPP_H18_IRQ 0x26
+#define GPP_H19_IRQ 0x27
+#define GPP_H20_IRQ 0x28
+#define GPP_H21_IRQ 0x29
+#define GPP_H22_IRQ 0x2A
+#define GPP_H23_IRQ 0x2B
/* Group D */
-#define GPP_D0_IRQ 0x28
-#define GPP_D1_IRQ 0x29
-#define GPP_D2_IRQ 0x2a
-#define GPP_D3_IRQ 0x2b
-#define GPP_D4_IRQ 0x2c
-#define GPP_D5_IRQ 0x2d
-#define GPP_D6_IRQ 0x2e
-#define GPP_D7_IRQ 0x2f
-#define GPP_D8_IRQ 0x30
-#define GPP_D9_IRQ 0x31
-#define GPP_D10_IRQ 0x32
-#define GPP_D11_IRQ 0x33
-#define GPP_D12_IRQ 0x34
-#define GPP_D13_IRQ 0x35
-#define GPP_D14_IRQ 0x36
-#define GPP_D15_IRQ 0x37
-#define GPP_D16_IRQ 0x38
-#define GPP_D17_IRQ 0x39
-#define GPP_D18_IRQ 0x3a
-#define GPP_D19_IRQ 0x3b
+#define GPP_D0_IRQ 0x2C
+#define GPP_D1_IRQ 0x2D
+#define GPP_D2_IRQ 0x2E
+#define GPP_D3_IRQ 0x2F
+#define GPP_D4_IRQ 0x30
+#define GPP_D5_IRQ 0x31
+#define GPP_D6_IRQ 0x32
+#define GPP_D7_IRQ 0x33
+#define GPP_D8_IRQ 0x34
+#define GPP_D9_IRQ 0x35
+#define GPP_D10_IRQ 0x36
+#define GPP_D11_IRQ 0x37
+#define GPP_D12_IRQ 0x38
+#define GPP_D13_IRQ 0x39
+#define GPP_D14_IRQ 0x3A
+#define GPP_D15_IRQ 0x3B
+#define GPP_D16_IRQ 0x3C
+#define GPP_D17_IRQ 0x3D
+#define GPP_D18_IRQ 0x3E
+#define GPP_D19_IRQ 0x3F
+
+
+/* Group U */
+#define GPP_U0_IRQ 0x40
+#define GPP_U1IRQ 0x41
+#define GPP_U2_IRQ 0x42
+#define GPP_U3_IRQ 0x43
+#define GPP_U4_IRQ 0x44
+#define GPP_U5_IRQ 0x45
+#define GPP_U6_IRQ 0x46
+#define GPP_U7_IRQ 0x47
+#define GPP_U8_IRQ 0x48
+#define GPP_U9_IRQ 0x49
+#define GPP_U10_IRQ 0x4A
+#define GPP_U11_IRQ 0x4B
+#define GPP_U12_IRQ 0x4C
+#define GPP_U13_IRQ 0x4D
+#define GPP_U14_IRQ 0x4E
+#define GPP_U15_IRQ 0x4F
+#define GPP_U16_IRQ 0x50
+#define GPP_U17_IRQ 0x51
+#define GPP_U18_IRQ 0x52
+#define GPP_U19_IRQ 0x53
-/* Group F */
-#define GPP_F0_IRQ 0x40
-#define GPP_F1_IRQ 0x41
-#define GPP_F2_IRQ 0x42
-#define GPP_F3_IRQ 0x43
-#define GPP_F4_IRQ 0x44
-#define GPP_F5_IRQ 0x45
-#define GPP_F6_IRQ 0x46
-#define GPP_F7_IRQ 0x47
-#define GPP_F8_IRQ 0x48
-#define GPP_F9_IRQ 0x49
-#define GPP_F10_IRQ 0x4a
-#define GPP_F11_IRQ 0x4b
-#define GPP_F12_IRQ 0x4c
-#define GPP_F13_IRQ 0x4d
-#define GPP_F14_IRQ 0x4e
-#define GPP_F15_IRQ 0x4f
-#define GPP_F16_IRQ 0x50
-#define GPP_F17_IRQ 0x51
-#define GPP_F18_IRQ 0x52
-#define GPP_F19_IRQ 0x53
-/* Group GPD */
-#define GPD0_IRQ 0x64
-#define GPD1_IRQ 0x65
-#define GPD2_IRQ 0x66
-#define GPD3_IRQ 0x67
-#define GPD4_IRQ 0x68
-#define GPD5_IRQ 0x69
-#define GPD6_IRQ 0x6a
-#define GPD7_IRQ 0x6b
-#define GPD8_IRQ 0x6c
-#define GPD9_IRQ 0x6d
-#define GPD10_IRQ 0x6e
-#define GPD11_IRQ 0x6f
+#define GPP_VGPIO4_IRQ 0x54
+
+/* Group F */
+#define GPP_F0_IRQ 0x56
+#define GPP_F1_IRQ 0x57
+#define GPP_F2_IRQ 0x58
+#define GPP_F3_IRQ 0x59
+#define GPP_F4_IRQ 0x5A
+#define GPP_F5_IRQ 0x5B
+#define GPP_F6_IRQ 0x5C
+#define GPP_F7_IRQ 0x5D
+#define GPP_F8_IRQ 0x5E
+#define GPP_F9_IRQ 0x5F
+#define GPP_F10_IRQ 0x60
+#define GPP_F11_IRQ 0x61
+#define GPP_F12_IRQ 0x62
+#define GPP_F13_IRQ 0x63
+#define GPP_F14_IRQ 0x64
+#define GPP_F15_IRQ 0x65
+#define GPP_F16_IRQ 0x66
+#define GPP_F17_IRQ 0x67
+#define GPP_F18_IRQ 0x68
+#define GPP_F19_IRQ 0x69
+#define GPP_F20_IRQ 0x6A
+#define GPP_F21_IRQ 0x6B
+#define GPP_F22_IRQ 0x6C
+#define GPP_F23_IRQ 0x6D
/* Group C */
-#define GPP_C0_IRQ 0x5a
-#define GPP_C1_IRQ 0x5b
-#define GPP_C2_IRQ 0x5c
-#define GPP_C3_IRQ 0x5d
-#define GPP_C4_IRQ 0x5e
-#define GPP_C5_IRQ 0x5f
-#define GPP_C6_IRQ 0x60
-#define GPP_C7_IRQ 0x61
-#define GPP_C8_IRQ 0x62
-#define GPP_C9_IRQ 0x63
-#define GPP_C10_IRQ 0x64
-#define GPP_C11_IRQ 0x65
-#define GPP_C12_IRQ 0x66
-#define GPP_C13_IRQ 0x67
-#define GPP_C14_IRQ 0x68
-#define GPP_C15_IRQ 0x69
-#define GPP_C16_IRQ 0x6a
-#define GPP_C17_IRQ 0x6b
-#define GPP_C18_IRQ 0x6c
-#define GPP_C19_IRQ 0x6d
-#define GPP_C20_IRQ 0x6e
-#define GPP_C21_IRQ 0x6f
-#define GPP_C22_IRQ 0x70
-#define GPP_C23_IRQ 0x71
-/* Group E */
-#define GPP_E0_IRQ 0x72
-#define GPP_E1_IRQ 0x73
-#define GPP_E2_IRQ 0x74
-#define GPP_E3_IRQ 0x75
-#define GPP_E4_IRQ 0x76
-#define GPP_E5_IRQ 0x77
-#define GPP_E6_IRQ 0x18
-#define GPP_E7_IRQ 0x19
-#define GPP_E8_IRQ 0x1a
-#define GPP_E9_IRQ 0x1b
-#define GPP_E10_IRQ 0x1c
-#define GPP_E11_IRQ 0x1d
-#define GPP_E12_IRQ 0x1e
-#define GPP_E13_IRQ 0x1f
-#define GPP_E14_IRQ 0x20
-#define GPP_E15_IRQ 0x21
-#define GPP_E16_IRQ 0x22
-#define GPP_E17_IRQ 0x23
-#define GPP_E18_IRQ 0x24
-#define GPP_E19_IRQ 0x25
-#define GPP_E20_IRQ 0x26
-#define GPP_E21_IRQ 0x27
-#define GPP_E22_IRQ 0x28
-#define GPP_E23_IRQ 0x29
+#define GPP_C0_iIRQ 0x6E
+#define GPP_C1_IRQ 0x6F
+#define GPP_C2_IRQ 0x70
+#define GPP_C3_IRQ 0x71
+#define GPP_C4_IRQ 0x72
+#define GPP_C5_IRQ 0x73
+#define GPP_C6_IRQ 0x74
+#define GPP_C7_IRQ 0x75
+#define GPP_C8_IRQ 0x76
+#define GPP_C9_IRQ 0x77
+#define GPP_C10_IRQ 0x18
+#define GPP_C11_IRQ 0x19
+#define GPP_C12_IRQ 0x1A
+#define GPP_C13_IRQ 0x1B
+#define GPP_C14_IRQ 0x1C
+#define GPP_C15_IRQ 0x1D
+#define GPP_C16_IRQ 0x1E
+#define GPP_C17_IRQ 0x1F
+#define GPP_C18_IRQ 0x20
+#define GPP_C19_IRQ 0x21
+#define GPP_C20_IRQ 0x22
+#define GPP_C21_IRQ 0x23
+#define GPP_C22_IRQ 0x24
+#define GPP_C23_IRQ 0x25
-/* Group R*/
-#define GPP_R0_IRQ 0x50
-#define GPP_R1_IRQ 0x51
-#define GPP_R2_IRQ 0x52
-#define GPP_R3_IRQ 0x53
-#define GPP_R4_IRQ 0x54
-#define GPP_R5_IRQ 0x55
-#define GPP_R6_IRQ 0x56
-#define GPP_R7_IRQ 0x57
-/* Group S */
-#define GPP_S0_IRQ 0x5c
-#define GPP_S1_IRQ 0x5d
-#define GPP_S2_IRQ 0x5e
-#define GPP_S3_IRQ 0x5f
-#define GPP_S4_IRQ 0x60
-#define GPP_S5_IRQ 0x61
-#define GPP_S6_IRQ 0x62
-#define GPP_S7_IRQ 0x63
+
+/* Group E */
+#define GPP_E0_IRQ 0x26
+#define GPP_E1_IRQ 0x27
+#define GPP_E2_IRQ 0x28
+#define GPP_E3_IRQ 0x29
+#define GPP_E4_IRQ 0x30
+#define GPP_E5_IRQ 0x31
+#define GPP_E6_IRQ 0x32
+#define GPP_E7_IRQ 0x33
+#define GPP_E8_IRQ 0x34
+#define GPP_E9_IRQ 0x35
+#define GPP_E10_IRQ 0x36
+#define GPP_E11_IRQ 0x37
+#define GPP_E12_IRQ 0x38
+#define GPP_E13_IRQ 0x39
+#define GPP_E14_IRQ 0x3A
+#define GPP_E15_IRQ 0x3B
+#define GPP_E16_IRQ 0x3C
+#define GPP_E17_IRQ 0x3D
+#define GPP_E18_IRQ 0x3E
+#define GPP_E19_IRQ 0x3F
+#define GPP_E20_IRQ 0x40
+#define GPP_E21_IRQ 0x41
+#define GPP_E22_IRQ 0x42
+#define GPP_E23_IRQ 0x43
/* Register defines. */
#define GPIO_MISCCFG 0x10
@@ -269,8 +310,9 @@
#define GPI_INT_EN_0 0x110
#define GPI_SMI_STS_0 0x180
#define GPI_SMI_EN_0 0x1A0
-#define PAD_CFG_BASE 0x600
+#define PAD_CFG_BASE 0x700
#define GPIORXSTATE_MASK 0x1
#define GPIORXSTATE_SHIFT 1
+#define GPIOTXSTATE_MASK 0x1
#endif
diff --git a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h
index 738e217cfd..62de63f740 100644
--- a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h
+++ b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h
@@ -12,10 +12,8 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-
#ifndef _SOC_TIGERLAKE_GPIO_SOC_DEFS_H_
#define _SOC_TIGERLAKE_GPIO_SOC_DEFS_H_
-
/*
* Most of the fixed numbers and macros are based on the GPP groups.
* The GPIO groups are accessed through register blocks called
@@ -34,259 +32,354 @@
#define GPP_C 0xB
#define GPP_E 0xC
-#define GPIO_NUM_GROUPS 11
-#define GPIO_MAX_NUM_PER_GROUP 24
+#define GPIO_MAX_NUM_PER_GROUP 27
+#define COMM_0 0
+#define COMM_1 1
+#define COMM_2 2
+/* GPIO community 3 is not exposed to be used and hence is skipped. */
+#define COMM_4 3
+#define COMM_5 4
/*
* GPIOs are ordered monotonically increasing to match ACPI/OS driver.
*/
-
-/* Group G */
-#define GPP_G0 0
-#define GPP_G1 1
-#define GPP_G2 2
-#define GPP_G3 3
-#define GPP_G4 4
-#define GPP_G5 5
-#define GPP_G6 6
-#define GPP_G7 7
-
/* Group B */
-#define GPP_B0 8
-#define GPP_B1 9
-#define GPP_B2 10
-#define GPP_B3 11
-#define GPP_B4 12
-#define GPP_B5 13
-#define GPP_B6 14
-#define GPP_B7 15
-#define GPP_B8 16
-#define GPP_B9 17
-#define GPP_B10 18
-#define GPP_B11 19
-#define GPP_B12 20
-#define GPP_B13 21
-#define GPP_B14 22
-#define GPP_B15 23
-#define GPP_B16 24
-#define GPP_B17 25
-#define GPP_B18 26
-#define GPP_B19 27
-#define GPP_B20 28
-#define GPP_B21 29
-#define GPP_B22 30
-#define GPP_B23 31
-#define GPIO_RSVD_0 32
-#define GPIO_RSVD_1 33
+#define GPP_B0 0
+#define GPP_B1 1
+#define GPP_B2 2
+#define GPP_B3 3
+#define GPP_B4 4
+#define GPP_B5 5
+#define GPP_B6 6
+#define GPP_B7 7
+#define GPP_B8 8
+#define GPP_B9 9
+#define GPP_B10 10
+#define GPP_B11 11
+#define GPP_B12 12
+#define GPP_B13 13
+#define GPP_B14 14
+#define GPP_B15 15
+#define GPP_B16 16
+#define GPP_B17 17
+#define GPP_B18 18
+#define GPP_B19 19
+#define GPP_B20 20
+#define GPP_B21 21
+#define GPP_B22 22
+#define GPP_B23 23
+#define GPP_B24 24 /* GSPI0_CLK_LOOPBK */
+#define GPP_B25 25 /* GSPI1_CLK_LOOPBK */
+
+/* Group T */
+#define GPP_T0 26
+#define GPP_T1 27
+#define GPP_T2 28
+#define GPP_T3 29
+#define GPP_T4 30
+#define GPP_T5 31
+#define GPP_T6 32
+#define GPP_T7 33
+#define GPP_T8 34
+#define GPP_T9 35
+#define GPP_T10 36
+#define GPP_T11 37
+#define GPP_T12 38
+#define GPP_T13 39
+#define GPP_T14 40
+#define GPP_T15 41
/* Group A */
-#define GPP_A0 34
-#define GPP_A1 35
-#define GPP_A2 36
-#define GPP_A3 37
-#define GPP_A4 38
-#define GPP_A5 39
-#define GPP_A6 40
-#define GPP_A7 41
-#define GPP_A8 42
-#define GPP_A9 43
-#define GPP_A10 44
-#define GPP_A11 45
-#define GPP_A12 46
-#define GPP_A13 47
-#define GPP_A14 48
-#define GPP_A15 49
-#define GPP_A16 50
-#define GPP_A17 51
-#define GPP_A18 52
-#define GPP_A19 53
-#define GPP_A20 54
-#define GPP_A21 55
-#define GPP_A22 56
-#define GPP_A23 57
+#define GPP_A0 42
+#define GPP_A1 43
+#define GPP_A2 44
+#define GPP_A3 45
+#define GPP_A4 46
+#define GPP_A5 47
+#define GPP_A6 48
+#define GPP_A7 49
+#define GPP_A8 50
+#define GPP_A9 51
+#define GPP_A10 52
+#define GPP_A11 53
+#define GPP_A12 54
+#define GPP_A13 55
+#define GPP_A14 56
+#define GPP_A15 57
+#define GPP_A16 58
+#define GPP_A17 59
+#define GPP_A18 60
+#define GPP_A19 61
+#define GPP_A20 62
+#define GPP_A21 63
+#define GPP_A22 64
+#define GPP_A23 65
+#define GPP_A24 66 /* ESPI_CLK_LOOPBK */
+
+#define NUM_GPIO_COM0_PADS (GPP_A24 - GPP_B0 + 1)
-#define NUM_GPIO_COM0_PADS (GPP_A23 - GPP_G0 + 1)
+/* Group S */
+#define GPP_S0 67
+#define GPP_S1 68
+#define GPP_S2 69
+#define GPP_S3 70
+#define GPP_S4 71
+#define GPP_S5 72
+#define GPP_S6 73
+#define GPP_S7 74
/* Group H */
-#define GPP_H0 58
-#define GPP_H1 59
-#define GPP_H2 60
-#define GPP_H3 61
-#define GPP_H4 62
-#define GPP_H5 63
-#define GPP_H6 64
-#define GPP_H7 65
-#define GPP_H8 66
-#define GPP_H9 67
-#define GPP_H10 68
-#define GPP_H11 69
-#define GPP_H12 70
-#define GPP_H13 71
-#define GPP_H14 72
-#define GPP_H15 73
-#define GPP_H16 74
-#define GPP_H17 75
-#define GPP_H18 76
-#define GPP_H19 77
-#define GPP_H20 78
-#define GPP_H21 79
-#define GPP_H22 80
-#define GPP_H23 81
+#define GPP_H0 75
+#define GPP_H1 76
+#define GPP_H2 77
+#define GPP_H3 78
+#define GPP_H4 79
+#define GPP_H5 80
+#define GPP_H6 81
+#define GPP_H7 82
+#define GPP_H8 83
+#define GPP_H9 84
+#define GPP_H10 85
+#define GPP_H11 86
+#define GPP_H12 87
+#define GPP_H13 88
+#define GPP_H14 89
+#define GPP_H15 90
+#define GPP_H16 91
+#define GPP_H17 92
+#define GPP_H18 93
+#define GPP_H19 94
+#define GPP_H20 95
+#define GPP_H21 96
+#define GPP_H22 97
+#define GPP_H23 98
/* Group D */
-#define GPP_D0 82
-#define GPP_D1 83
-#define GPP_D2 84
-#define GPP_D3 85
-#define GPP_D4 86
-#define GPP_D5 87
-#define GPP_D6 88
-#define GPP_D7 89
-#define GPP_D8 90
-#define GPP_D9 91
-#define GPP_D10 92
-#define GPP_D11 93
-#define GPP_D12 94
-#define GPP_D13 95
-#define GPP_D14 96
-#define GPP_D15 97
-#define GPP_D16 98
-#define GPP_D17 99
-#define GPP_D18 100
-#define GPP_D19 101
-#define GPIO_RSVD_2 102
+#define GPP_D0 99
+#define GPP_D1 100
+#define GPP_D2 101
+#define GPP_D3 102
+#define GPP_D4 103
+#define GPP_D5 104
+#define GPP_D6 105
+#define GPP_D7 106
+#define GPP_D8 107
+#define GPP_D9 108
+#define GPP_D10 109
+#define GPP_D11 110
+#define GPP_D12 111
+#define GPP_D13 112
+#define GPP_D14 113
+#define GPP_D15 114
+#define GPP_D16 115
+#define GPP_D17 116
+#define GPP_D18 117
+#define GPP_D19 118
+#define GPP_GSPI2_CLK_LOOPBK 119
-/* Group F */
-#define GPP_F0 103
-#define GPP_F1 104
-#define GPP_F2 105
-#define GPP_F3 106
-#define GPP_F4 107
-#define GPP_F5 108
-#define GPP_F6 109
-#define GPP_F7 110
-#define GPP_F8 111
-#define GPP_F9 112
-#define GPP_F10 113
-#define GPP_F11 114
-#define GPP_F12 115
-#define GPP_F13 116
-#define GPP_F14 117
-#define GPP_F15 118
-#define GPP_F16 119
-#define GPP_F17 120
-#define GPP_F18 121
-#define GPP_F19 122
+/* Group U */
+#define GPP_U0 120
+#define GPP_U1 121
+#define GPP_U2 122
+#define GPP_U3 123
+#define GPP_U4 124
+#define GPP_U5 125
+#define GPP_U6 126
+#define GPP_U7 127
+#define GPP_U8 128
+#define GPP_U9 129
+#define GPP_U10 130
+#define GPP_U11 131
+#define GPP_U12 132
+#define GPP_U13 133
+#define GPP_U14 134
+#define GPP_U15 135
+#define GPP_U16 136
+#define GPP_U17 137
+#define GPP_U18 138
+#define GPP_U19 139
+#define GPP_GSPI3_CLK_LOOPBK 140
+#define GPP_GSPI4_CLK_LOOPBK 141
+#define GPP_GSPI5_CLK_LOOPBK 142
+#define GPP_GSPI6_CLK_LOOPBK 143
-#define NUM_GPIO_COM1_PADS (GPP_F19 - GPP_H0 + 1)
+/* Group VGPIO */
+#define CNV_BTEN 144
+#define CNV_BT_HOST_WAKEB 145
+#define CNV_BT_IF_SELECT 146
+#define vCNV_BT_UART_TXD 147
+#define vCNV_BT_UART_RXD 148
+#define vCNV_BT_UART_CTS_B 149
+#define vCNV_BT_UART_RTS_B 150
+#define vCNV_MFUART1_TXD 151
+#define vCNV_MFUART1_RXD 152
+#define vCNV_MFUART1_CTS_B 153
+#define vCNV_MFUART1_RTS_B 154
+#define vUART0_TXD 155
+#define vUART0_RXD 156
+#define vUART0_CTS_B 157
+#define vUART0_RTS_B 158
+#define vISH_UART0_TXD 159
+#define vISH_UART0_RXD 160
+#define vISH_UART0_CTS_B 161
+#define vISH_UART0_RTS_B 162
+#define vCNV_BT_I2S_BCLK 163
+#define vCNV_BT_I2S_WS_SYNC 164
+#define vCNV_BT_I2S_SDO 165
+#define vCNV_BT_I2S_SDI 166
+#define vI2S2_SCLK 167
+#define vI2S2_SFRM 168
+#define vI2S2_TXD 169
+#define vI2S2_RXD 170
+#define NUM_GPIO_COM1_PADS (vI2S2_RXD - GPP_S0 + 1)
/* Group GPD */
-#define GPD0 123
-#define GPD1 124
-#define GPD2 125
-#define GPD3 126
-#define GPD4 127
-#define GPD5 128
-#define GPD6 129
-#define GPD7 130
-#define GPD8 131
-#define GPD9 132
-#define GPD10 133
-#define GPD11 134
-
-#define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1)
+#define GPD0 171
+#define GPD1 172
+#define GPD2 173
+#define GPD3 174
+#define GPD4 175
+#define GPD5 176
+#define GPD6 177
+#define GPD7 178
+#define GPD8 179
+#define GPD9 180
+#define GPD10 181
+#define GPD11 182
+#define GPD_INPUT3VSEL 183
+#define GPD_SLP_LANB 184
+#define GPD__SLP_SUSB 185
+#define GPD_WAKEB 186
+#define GPD_DRAM_RESETB 187
+#define NUM_GPIO_COM2_PADS (GPD_DRAM_RESETB - GPD0 + 1)
/* Group C */
-#define GPP_C0 135
-#define GPP_C1 136
-#define GPP_C2 137
-#define GPP_C3 138
-#define GPP_C4 139
-#define GPP_C5 140
-#define GPP_C6 141
-#define GPP_C7 142
-#define GPP_C8 143
-#define GPP_C9 144
-#define GPP_C10 145
-#define GPP_C11 146
-#define GPP_C12 147
-#define GPP_C13 148
-#define GPP_C14 149
-#define GPP_C15 150
-#define GPP_C16 151
-#define GPP_C17 152
-#define GPP_C18 153
-#define GPP_C19 154
-#define GPP_C20 155
-#define GPP_C21 156
-#define GPP_C22 157
-#define GPP_C23 158
-#define GPIO_RSVD_3 159
-#define GPIO_RSVD_4 160
-#define GPIO_RSVD_5 161
-#define GPIO_RSVD_6 162
-#define GPIO_RSVD_7 163
-#define GPIO_RSVD_8 164
+#define GPP_C0 188
+#define GPP_C1 189
+#define GPP_C2 190
+#define GPP_C3 191
+#define GPP_C4 192
+#define GPP_C5 193
+#define GPP_C6 194
+#define GPP_C7 195
+#define GPP_C8 196
+#define GPP_C9 197
+#define GPP_C10 198
+#define GPP_C11 199
+#define GPP_C12 200
+#define GPP_C13 201
+#define GPP_C14 202
+#define GPP_C15 203
+#define GPP_C16 204
+#define GPP_C17 205
+#define GPP_C18 206
+#define GPP_C19 207
+#define GPP_C20 208
+#define GPP_C21 209
+#define GPP_C22 210
+#define GPP_C23 211
+
+/* Group F */
+#define GPP_F0 212
+#define GPP_F1 213
+#define GPP_F2 214
+#define GPP_F3 215
+#define GPP_F4 216
+#define GPP_F5 217
+#define GPP_F6 218
+#define GPP_F7 219
+#define GPP_F8 220
+#define GPP_F9 221
+#define GPP_F10 222
+#define GPP_F11 223
+#define GPP_F12 224
+#define GPP_F13 225
+#define GPP_F14 226
+#define GPP_F15 227
+#define GPP_F16 228
+#define GPP_F17 229
+#define GPP_F18 230
+#define GPP_F19 231
+#define GPP_F20 232
+#define GPP_F21 233
+#define GPP_F22 234
+#define GPP_F23 235
+#define GPP_F_CLK_LOOPBK 236
+
+/* Group HVCMOS */
+#define GPP_L_BKLTEN 237
+#define GPP_L_BKLTCTL 238
+#define GPP_L_VDDEN 239
+#define GPP_SYS_PWROK 240
+#define GPP_SYS_RESETB 241
+#define GPP_MLK_RSTB 242
/* Group E */
-#define GPP_E0 165
-#define GPP_E1 166
-#define GPP_E2 167
-#define GPP_E3 168
-#define GPP_E4 169
-#define GPP_E5 170
-#define GPP_E6 171
-#define GPP_E7 172
-#define GPP_E8 173
-#define GPP_E9 174
-#define GPP_E10 175
-#define GPP_E11 176
-#define GPP_E12 177
-#define GPP_E13 178
-#define GPP_E14 179
-#define GPP_E15 180
-#define GPP_E16 181
-#define GPP_E17 182
-#define GPP_E18 183
-#define GPP_E19 184
-#define GPP_E20 185
-#define GPP_E21 186
-#define GPP_E22 187
-#define GPP_E23 188
+#define GPP_E0 243
+#define GPP_E1 244
+#define GPP_E2 245
+#define GPP_E3 246
+#define GPP_E4 247
+#define GPP_E5 248
+#define GPP_E6 249
+#define GPP_E7 250
+#define GPP_E8 251
+#define GPP_E9 252
+#define GPP_E10 253
+#define GPP_E11 254
+#define GPP_E12 255
+#define GPP_E13 256
+#define GPP_E14 257
+#define GPP_E15 258
+#define GPP_E16 259
+#define GPP_E17 260
+#define GPP_E18 261
+#define GPP_E19 262
+#define GPP_E20 263
+#define GPP_E21 264
+#define GPP_E22 265
+#define GPP_E23 266
+#define GPP_E_CLK_LOOPBK 267
-#define NUM_GPIO_COM4_PADS (GPP_E23 - GPP_C0 + 1)
+/* Group JTAG */
+#define GPP_JTAG_TDO 268
+#define GPP_JTAG_X 269
+#define GPP_JTAG_PRDYB 270
+#define GPP_JTAG_PREQB 271
+#define GPP_CPU_TRSTB 272
+#define GPP_JTAG_TDI 273
+#define GPP_JTAG_TMS 274
+#define GPP_JTAG_TCK 275
+#define GPP_DBG_PMODE 276
-/* Group R*/
-#define GPP_R0 189
-#define GPP_R1 190
-#define GPP_R2 191
-#define GPP_R3 192
-#define GPP_R4 193
-#define GPP_R5 194
-#define GPP_R6 195
-#define GPP_R7 196
+#define NUM_GPIO_COM4_PADS (GPP_DBG_PMODE - GPP_C0 + 1)
-/* Group S */
-#define GPP_S0 197
-#define GPP_S1 198
-#define GPP_S2 199
-#define GPP_S3 200
-#define GPP_S4 201
-#define GPP_S5 202
-#define GPP_S6 203
-#define GPP_S7 204
+/* Group R */
+#define GPP_R0 277
+#define GPP_R1 278
+#define GPP_R2 279
+#define GPP_R3 280
+#define GPP_R4 281
+#define GPP_R5 282
+#define GPP_R6 283
+#define GPP_R7 284
-#define NUM_GPIO_COM5_PADS (GPP_S7 - GPP_R0 + 1)
+/* Group SPI */
+#define GPP_SPI_IO_2 285
+#define GPP_SPI_IO_3 286
+#define GPP_SPI_MOSI_IO_0 287
+#define GPP_SPI_MOSI_IO_1 288
+#define GPP_SPI_TPM_CSB 289
+#define GPP_SPI_FLASH_0_CSB 290
+#define GPP_SPI_FLASH_1_CSB 291
+#define GPP_SPI_CLK 292
+#define GPP_CLK_LOOPBK 293
-#define TOTAL_PADS 205
+#define NUM_GPIO_COM5_PADS (GPP_CLK_LOOPBK - GPP_R0 + 1)
-#define COMM_0 0
-#define COMM_1 1
-#define COMM_2 2
-#define COMM_3 3
-#define COMM_4 4
-#define TOTAL_GPIO_COMM 5
+#define TOTAL_GPIO_COMM (COMM_5 + 1)
+#define TOTAL_PADS 294
#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 22:50:52 +0000